參數(shù)資料
型號(hào): MT54W4MH8BF-7.5
廠商: Micron Technology, Inc.
英文描述: 36Mb QDR⑩II SRAM 2-WORD BURST
中文描述: ⑩分配36MB四年防務(wù)審查II SRAM的2字爆
文件頁(yè)數(shù): 22/27頁(yè)
文件大?。?/td> 302K
代理商: MT54W4MH8BF-7.5
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
22
2002, Micron Technology Inc.
Figure 9
TAP Timing
tTLTH
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTHTL
Test Data-Out
(TDO)
tTHTH
Test Data-In
(TDI)
tTHMX
tMVTH
tTHDX
tDVTH
tTLOX
tTLOV
DON’T CARE
UNDEFINED
TAP DC ELECTRICAL CHARACTERISTICS
1,2
0oC T
A
+70oC;
+1.7V V
DD
+1.9V
DESCRIPTION
Clock
Clock cycle time
SYMBOL
MIN
MAX
UNITS
t
THTH
f
TF
t
THTL
t
TLTH
100
ns
Clock frequency
10
MHz
Clock HIGH time
40
ns
Clock LOW time
Output Times
TCK LOW to TDO unknown
40
ns
t
TLOX
t
TLOV
t
DVTH
t
THDX
0
ns
TCK LOW to TDO valid
20
ns
TDI valid to TCK HIGH
10
ns
TCK HIGH to TDI invalid
Setup Times
TMS setup
10
ns
t
MVTH
t
CS
10
ns
Capture setup
Hold Times
TMS hold
10
ns
t
THMX
t
CH
10
ns
Capture hold
10
ns
NOTE:
1.
t
CS and
t
CH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 10.
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MT54W4MH9B-7.5 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST