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參數(shù)資料
| 型號(hào)： | MT54W4MH8BF-6 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 中文描述： | ⑩分配36MB四年防務(wù)審查II SRAM的2字爆 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MT54W4MH8BF-6 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
2002, Micron Technology Inc.
Figure 4
Bus Cycle State Diagram
NOTE:
1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx .
. . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2).
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active.
4. State machine control timing sequence is controlled by K.
LOAD NEW
READ ADDRESS
READ DOUBLE
POWER-UP
Supply voltage
provided
READ PORT NOP
R_Init=0
RD
RD
always
/RD
/RD
LOAD NEW
WRITE ADDRESS
AT K#
↑
WRITE DOUBLE
AT K#
↑
Supply voltage
provided
WRITE PORT NOP
WT
WT
always
/WT
/WT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT54W4MH8BF-7.5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-4 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-6 | 36Mb QDR⑩II SRAM 2-WORD BURST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54W4MH8BF-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
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