參數(shù)資料
型號(hào): MT4LC8M8E1TG-5
廠商: Micron Technology, Inc.
英文描述: DRAM
中文描述: 內(nèi)存
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 382K
代理商: MT4LC8M8E1TG-5
6
8 Meg x 8 FPM DRAM
D19_2.p65
Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
8 MEG x 8
FPM DRAM
CAPACITANCE
(Note: 2)
PARAMETER
Input Capacitance: Address pins
Input Capacitance: RAS#, CAS#, WE#, OE#
Input/Output Capacitance: DQ
SYMBOL
C
I
1
C
I
2
C
IO
MAX
5
7
7
UNITS
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (V
CC
= +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to
Don
t Care
during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CAS# precharge time (FAST PAGE MODE)
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable time
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
-5
-6
SYMBOL
t
AA
t
AR
t
ASC
t
ASR
t
AWD
t
CAC
t
CAH
t
CAS
t
CHD
t
CHR
t
CLZ
t
CP
t
CPA
t
CRP
t
CSH
t
CSR
t
CWD
t
CWL
t
DH
t
DS
t
OD
t
OE
t
OEH
MIN
MAX
25
MIN
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
40
0
0
48
45
0
0
55
18
13
15
8
13
15
15
3
8
10
15
15
15
3
10
10,000
10,000
4
13
30
35
5
50
5
36
13
8
0
3
5
60
5
40
15
10
0
3
4
18
19
19
13
13
15
15
23, 24
20
24
13
15
t
OFF
t
ORD
3
0
13
3
0
15
ns
ns
17, 23
t
PC
30
76
35
85
ns
ns
ns
t
PRWC
t
RAC
50
60
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