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參數(shù)資料
| 型號： | MT4C4M4B1TG-6 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DRAM |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 360K |
| 代理商： | MT4C4M4B1TG-6 |
8
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
CC
= +3.3V or 5.0V;
f = 1 MHz.
3.
I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with
minimum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured.
6.
An initial pause of 100μs is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
7.
AC characteristics assume
t
T = 5ns.
8.
V
IH
(MIN) and V
IL
(MAX ) are reference levels for
measuring timing of input signals. Transition
times are measured between V
IH
and V
IL
(or
between V
IL
and V
IH
).
9.
In addition to meeting the transition rate
specification, all input signals must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in
a monotonic manner.
10. If CAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data
from the last valid READ cycle.
12. Measured with a load equivalent to two TTL
gates, 100pF and V
OL
= 0.8V and V
OH
= 2V.
13. If CAS# is LOW at the falling edge of RAS#, Q
will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out
buffer, CAS# must be pulsed HIGH for
t
CP.
14. The
t
RCD (MAX ) limit is no longer specified.
t
RCD (MAX ) was specified as a reference point
only. If
t
RCD was greater than the specified
t
RCD (MAX ) limit, then access time was con-
trolled exclusively by
t
CAC (
t
RAC [MIN] no
longer applied). With or without the
t
RCD limit,
t
AA and
t
CAC must always be met.
15. The
t
RAD (MAX ) limit is no longer specified.
t
RAD (MAX ) was specified as a reference point
only. If
t
RAD was greater than the specified
t
RAD (MAX ) limit, then access time was con-
trolled exclusively by
t
AA (
t
RAC and
t
CAC no
longer applied). With or without the
t
RAD
(MAX ) limit,
t
AA,
t
RAC, and
t
CAC must always
be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX ) defines the time at which the
output achieves the open circuit condition and
is not referenced to V
OH
or V
OL
.
18.
t
WCS,
t
RWD,
t
AWD, and
t
CWD are not
restrictive operating parameters.
t
WCS applies to
EARLY WRITE cycles.
t
RWD,
t
AWD, and
t
CWD
apply to READ-MODIFY-WRITE cycles. If
t
WCS
t
WCS (MIN), the cycle is an EARLY WRITE
cycle and the data output will remain an open
circuit throughout the entire cycle. If
t
RWD
3
t
RWD (MIN),
t
AWD
3
t
AWD (MIN), and
t
CWD
3
t
CWD (MIN), the cycle is a READ-MODIFY-
WRITE and the data output will contain data
read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD, and
t
AWD are not applicable in a LATE
WRITE cycle.
19. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
20. If OE# is tied permanently LOW, LATE WRITE,
or READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
21. A HIDDEN REFRESH may also be performed
after a WRITE cycle. In this case, WE# = LOW
and OE# = HIGH.
22. The 3ns minimum is a parameter guaranteed by
design.
23. Column address changed once each cycle.
24. V
IH
overshoot: V
IH
(MAX ) = V
CC
+ 2V for a pulse
width
￡
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
￡
10ns, and the pu lse width cannot be greater
than one third of the cycle rate.
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