- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384755 > MT48LC64M8A2 (Micron Technology, Inc.) SYNCHRONOUS DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | MT48LC64M8A2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 25/55頁 |
| 文件大?。?/td> | 1828K |
| 代理商： | MT48LC64M8A2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
25
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65
–
Rev. D; Pub 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
SDRAM
ADVANCE
CONCURRENT AUTO PRECHARGE
An access command to (READ or WRITE) another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with auto precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank
m
will interrupt a READ
on bank
n
, CAS latency later. The PRECHARGE to
bank
n
will begin when the READ to bank
m
is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank
m
will interrupt a READ
on bank
n
when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank
n
will begin
when the WRITE to bank
m
is registered (Figure 25).
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK
n
NOP
NOP
NOP
NOP
D
OUT
a
+ 1
D
OUT
d
D
OUT
d
+ 1
NOP
T7
BANK
n
CAS Latency = 3 (BANK
m
)
BANK
m
ADDRESS
Idle
NOP
NOTE:
DQM is LOW.
BANK
n
,
COL
a
BANK
m
,
COL
d
READ - AP
BANK
m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK
n
tRP - BANK
m
CAS Latency = 3 (BANK
n
)
Figure 24
READ With Auto Precharge Interrupted by a READ
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
NOP
NOP
NOP
D
IN
d
+ 1
D
IN
d
D
IN
d
+ 2
D
IN
d
+ 3
NOP
T7
BANK
n
BANK
m
ADDRESS
Idle
NOP
DQM
NOTE:
1. DQM is HIGH at T2 to prevent D
OUT
-
a
+1 from contending with D
IN
-
d
at T4.
BANK
n
,
COL
a
BANK
m
,
COL
d
WRITE - AP
BANK
m
Internal
States
t
Page
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP -
BANK
n
tWR -
BANK
m
CAS Latency = 3 (BANK
n
)
READ - AP
BANK
n
1
DON
’
T CARE
Figure 25
READ With Auto Precharge Interrupted by a WRITE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48LC32M16A2 | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-75LIT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7E | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7EIT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7EL | SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。