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參數(shù)資料
| 型號： | MT352GP1N |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | COFDM Demodulator |
| 中文描述： | COFDM解調(diào)器 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 478K |
| 代理商： | MT352GP1N |
MT352
Data Sheet
13
Zarlink Semiconductor Inc.
drive a LED to show the status of a range of different internal lock flags. Alternatively, it can drive an audio
transducer to give an audio frequency that is dependent upon the error rate of the received signal.
This feature can be used for faster installation of a system where the aerial may need to be adjusted, as signal
strength is not the best guide for the optimum aerial position for COFDM reception.
3.1 2-Wire Bus
3.2 Host
The primary 2-wire bus serial interface uses pins:
The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.
DATA1 (pin 5) serial data, the most significant bit is sent first.
CLK1 (pin 4) serial clock.
In the current TNIM evaluation application, the 2-wire bus address is 0001 111 R/ W with the pins connected as
follows:
When the MT352 is powered up, the RESET pin 28 should be held low for at least 50ms after VDD has reached
normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus
address. ADDR[0] is the R/ W bit.
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive
mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD
register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following
byte. Not all addresses are valid and many are reserved registers that must not be changed from their default
values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access
the reserved registers accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address
is not recognized, the MT352 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could next be followed with a write command to continue from the latest address. RADD would not be sent in this
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.
3.2.1 Tuner
The MT352 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. Master control
mode is selected by a single register control bit.
The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
Not programmable
SADD[4]
SADD[3]
SADD[2]
SADD[1]
SADD[0]
VSS
VSS
VSS
VDD
VDD
VDD
VDD
Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application
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相關代理商/技術參數(shù) |
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|---|---|
| MT3530 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:BELL 103/V.21 SINGLE CHIP MODEM |
| MT3530BE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:BELL 103/V.21 SINGLE CHIP MODEM |
| MT3560A-UHR2 | 制造商:MARKTECH 制造商全稱:Marktech Corporate 功能描述:Red Visible Emitter |
| MT35-H | 制造商:Tamura Corporation of America 功能描述: |
| MT35-M | 制造商:Tamura Corporation of America 功能描述: |
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