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參數(shù)資料
| 型號(hào)： | MT312T-Y |
| 廠商： | Marktech Optoelectronics |
| 英文描述： | 2x4mm Rectangular LED Lamps |
| 中文描述： | 2x4mm矩形發(fā)光二極管 |
| 文件頁(yè)數(shù)： | 21/90頁(yè) |
| 文件大?。?/td> | 318K |
| 代理商： | MT312T-Y |
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Initialisation
MT312
21
3.5 MT312 Initialisation Read/Write Registers
3.5.1 Reset. Register 21 (R/W)
B7:
FR 312
High = Full reset of MT312 device.
B6:
PR 312
High = Partial reset of MT312 device.
B5:
FR QP
High = Full reset of QPSK block.
B4:
PR QP
High = Partial reset of QPSK block.
B3:
FR VIT
High = Full reset of Viterbi block.
B2:
PR VIT
High = Partial reset of Viterbi block.
B1:
PR BA
High = Partial reset of Byte Align block.
B0:
PR DS
High = Partial reset of De-scrambler block.
Writing a one to these register locations generates a reset pulse three crystal clock periods wide.
The register automatically resets to zero after use.
A full reset does reset the registers to their default values.
A partial reset does not reset the registers to their default values.
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Def
hex
RESET
21
FR
312
PR
312
FR
QP
PR
QP
FR
VIT
PR
VIT
PR
BA
PR
DS
R/W
00
3.4 Spectral Inversion
Spectral inversion of the QPSK signal can be caused
by the transmitter or the receiver front-end. In the
latter case, this could happen due to the way I-Q
conversion is carried out or because the I and Q
wires are swapped between the I-Q converter and
the MT312. If spectral inversion is caused by the
receiver front-end, then this must be removed by
swapping I and Q (within MT312) before QPSK
demodulation, by setting Q IQ SP bit B6 of QPSK
CTRL register (26) to 1.
If no spectral inversion is caused by the receiver
front-end design, then bit B6 of QPSK CTRL must
always be held at zero. If the transmitted signal is
known to be spectrally inverted, then V IQ SP bit B6
of the VIT MODE register (25) must be set to 1. Then
I and Q are swapped after QPSK demodulation. If
the spectral inversion status of the transmitted signal
is not known, then after QPSK has locked (i.e. QPSK
CT LOCK = 1), the software must try to achieve FEC
lock with the bit B6 of VIT MODE register
fi
rst at zero
and then at one.
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