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參數(shù)資料
| 型號(hào)： | MSX532 |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | DSP-CROSSBAR SWITCH, PBGA792 |
| 封裝： | PLASTIC, BGA-792 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 139K |
| 代理商： | MSX532 |
MSX532 Mini Data Sheet
Matrix Switching Crossbar Device
Last Modified: November 8, 1999
PRELIMINARY
MSX532 FEATURES
SRAM-based, in-system programmable
3.3V operation, LVTTL I/O’s (5V tolerant)
Switch Matrix
Non-blocking: One-to-One and One-to-Many
connections
Double-buffered configuration RAM cells for
simultaneous global updates
532 Configurable I/O Ports
Individually programmable as input, output,
bi-directional, or Bus Repeater mode
Control Signals per I/O pin: 2 input enable
pins, 2 output enable pins, 3 clock pins (2
clock sources plus 1 clock from the next-
neighbor pin)
Output data inversion: capable of inverting
output signals
Registered and Flow-through data modes
200MHz clock frequency in registered mode
300Mbps in Flow-through mode
5ns propagation delay in Flow-through mode
Less than 1ns output-to-output skew
Programmable output slew rate
8mA output current
Dedicated RapidConfigure parallel interface, as
well as JTAG serial interface for configuration and
readback of both the I/O Buffers and Switch
Matrix status
792-pin PBGA package
DESCRIPTION
The
MSX
family
of
SRAM-based
bit-oriented
switching devices is manufactured using a 0.35
CMOS process. The devices offer flow-through NRZ
datarates of 300Mbps and registered clock frequencies
of 200MHz. The 532 I/O Buffers (IOB’s) are
individually configured. The IOBs can be connected to
each other through the switch matrix, which supports
One-to-One and One-to-Many connections.
The proprietary RapidConfigure parallel interface
allows fast configuration of both the IOBs and switch
matrix. It also allows a readback of the device for test
and verification purposes. The MSX532 also supports
the industry standard JTAG (IEEE 1149.1) interface
for boundary scan testing. The same interface can also
be used to serially download configuration data to the
MSX532 device. The functional block diagram is
shown in Figure 1.
APPLICATIONS
Telecom and datacom switching
Video switches and servers
Test equipment
CLK_0
IE_0
OE_0
OE_2
IE_2
CLK_2
P266–P398
OE_3
IE_3
CLK_3
P399–P531
CLK_1
IE_1
OE_1
P133–P265
P0–P132
N
S
WE
Figure 1: MSX Functional Block Diagram
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參數(shù)描述 |
|---|---|
| MSX532 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| MSX532TB792 | 功能描述:模擬和數(shù)字交叉點(diǎn) IC RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| MSX5542 | 制造商:Cinch Connectors 功能描述: |
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| MSX6-540 | 制造商:Cinch Connectors 功能描述: |
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