參數(shù)資料
型號(hào)： MSM98S
廠商： Electronic Theatre Controls, Inc.
英文描述： 0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays
中文描述： 0.8混合3-V/5-V海蓋茨和客戶結(jié)構(gòu)陣列
文件頁(yè)數(shù)： 15/23頁(yè)
文件大?。?/td> 96K
代理商： MSM98S
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I
MSM38S/98S Data Sheet
I
13
OKI SEMICONDUCTOR
DESIGN PROCESS
Figure 8. OKI Design Process
Floorplanning
CDC
[1]
Floorplanning
Scan Insertion (Optional)
CDC
[1]
Fault Simulation
[5]
(Cadence Verifault or IKOS)
Schematics
Test Vectors
VHDL/HDL Description
Test Vector Conversion
(OKI TPL
)
Netlist Conversion
(EDIF 200)
TDC
[2]
Pre-Layout Simulation
(Cadence Verilog)
Layout
(Silvar Lisco Gards)
Automatic Test
Vector Generation
(Synopsys Test Compiler)
Verification
(Cadence DRACULA)
Post-Layout Simulation
(Cadence Verilog)
Manufacturing
Prototype
Test Program
Conversion
Level 1
[4]
Level 2
Level 2.5
[4]
Level 3
[4]
CAE Front-End
OKI Interface
[1] OKI Circuit Data Check program (CDC) verifies logic design rules
[2] OKI Test Data Check program (TDC) verifies test vector rules
[3] OKI Test Pattern Language (TPL)
[4] Alternate Customer-OKI design interfaces available in addition to standard level 2
[5] Standard design process includes fault simulation
Simulation
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