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參數(shù)資料
| 型號： | MSM98S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays |
| 中文描述： | 0.8混合3-V/5-V海蓋茨和客戶結構陣列 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 96K |
| 代理商： | MSM98S |
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
I
MSM38S/98S Data Sheet
I
11
OKI SEMICONDUCTOR
Dynamic sub-trunk allocation
Single clock tree driver logic symbol
Single-level clock drivers
Automatic branch length minimization
Dynamic driver placement
Up to four clock trunks
The clock-skew management scheme is described in detail in the
0.8μm Technology
Clock Skew Management
Application Note
.
Figure 5. Clock Tree Structure
OUTPUT DRIVER MACROCELLS FOR SLEW RATE CONTROL
The slew-rate-control output driver macrocells reduce both simultaneous-switching noise and output-
ringing noise. The output transistors are split into two sets; first, one set of output transistors drive the
output pads, then, after the output passes the threshold, the second set of output transistors drive the I/ O
pads.
Figure 6
below shows output drivers configured for slew-rate control. All outputs with a drive of 8 mA or
more are available with slew-rate control.
Figure 6. Slew Rate Control Output Buffer
Clock Tree
Driver Macrocell
Clock Drivers
Sub Trunk
Clocked Cell
Input Buffer
Pad
Branch
Main Trunk
Switch
Output Pad
Second Set of
Output Transistors
First Set of
Output Transistors
From Internal Node
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