參數(shù)資料
型號(hào)： MSM9225
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： CAN (Controller Area Network) Controller
中文描述： CAN（控制器局域網(wǎng)）控制器
文件頁(yè)數(shù)： 57/74頁(yè)
文件大小： 488K
代理商： MSM9225
Semiconductor
MSM9225
60/73
(3) Data bit synchronization
Since there is no sync signal for the receive node, synchronization is obtained from level
changes on the bus.
The transmit node transmits data is synchronization with the transmit node bit timing.
(a) Hardware synchronization
Hardware synchronizaion is the bit synchronization performed when a receive node in the bus
idle state detects a start-of-frame.
If a falling edge is detected on the bus, that bit is the sync segment and is followed by the prop
segment. In this case, syncronization is obtained without regard for SJW.
After reset and after wake up, it is necessary to obtain bit synchronization.
Therefore, hardware synchronizes to the first bus level change only.
Start-of-frame
Bus idle
CAN bus
Sync segment Prop segment
Phase
segment 1
Phase
segment 2
Bit timing
(b) Bit synchronization
If a level change is detected on the bus during receprion, bit synchronization is obtained.
There are two methods of synchronization.
Normal operation: falling edge of level
Low-speed operation: falling edge and rising edge of level
During the bit timing interval specified by SJW, synchronization is obtained only if an edge is
detected.
The data sampling point of the receive node will move in relation to the shift in baud rate
between the transmit node and receive node.
The range of allowable "shift" is defined as "SJW". The SJW range is centered on the sync
segment and extends both before and after that segment (+/– baud rate). If an edge occurs
within the SJW range, synchronization is obtained.
If an edge occurs outside the SJW range, synchronization is not obtained.
The bit detected at the edge forces the sync segment, and is followed by the prop segment.
The bit timing is restarted.
Later bits
Previous bits
CAN bus
Sync segment Prop segment
Phase
segment 1
Phase
segment 2
Bit timing
SJW
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