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參數(shù)資料
| 型號： | MSM832JLM-025 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 25 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 72K |
| 代理商： | MSM832JLM-025 |
MSM832 - 020/025/35
ISSUE 5.0 April 2001
1
32K x 8 SRAM
MSM832 - 020/025/35
Issue 5.0 : April 2001
31
W
E
32
V
c
15
D
2
1
6
GN
D
4
A7
1
N
C
2
A1
4
3
A1
2
30
A
1
3
J,W
PACKAGE
TOP VIEW
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
NC
12
D0
13
27
A11
26
NC
25
OE
24
A10
23
CS
22
D7
21
D6
28
A9
29
A8
20
D
5
17
N
C
18
D
3
19
D
4
14
D
1
Memory Array
512 X 512
Row
Decoder
X
Address
Buffer
I/O
Buffer
Column I/O
Column Decoder
Y Address Buffer
A3
A4
A5
A6
A7
A8
A12
A13
A14
D0
D7
CS
WE
OE
A0
A1
A2
A9
A1
0
A1
1
Description
The MSM832 is a high speed Static RAM organ-
ised as 32K x 8 available with access times of 20
25 or 35 ns. The device is available in four ce-
ramic package options including the high denisty
VIL package. It features completely static
operation with a low power standby mode and is
3.0V battery back-up compatible. It is directly TTL
compatible and has common data inputs and
outputs.
The device may be screened in accordance with
MIL-STD-883.
32,768 x 8 CMOS High Speed Static RAM
Features
Fast Access Times of 20/25/35 ns.
JEDEC Standard footprint.
Operating Power
908 mW (max)
Low Power Standby 11 mW (max) -L version.
Low Voltage Data Retention.
Directly TTL compatible.
Completely Static Operation.
Pin Functions
A0-A14
Address inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
Power(+5V)
GND
Ground
Pin Definitions
Block Diagram
Package Details
Pin Count
Description
Package Type
32
J-Leaded Chip Carrier (JLCC)
J
32
Leadless Chip Carrier (LCC)
W
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