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參數(shù)資料
| 型號： | MSC8126 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Digital Signal Processor |
| 中文描述： | 四路數(shù)字信號處理器 |
| 文件頁數(shù)： | 40/48頁 |
| 文件大?。?/td> | 792K |
| 代理商： | MSC8126 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Hardware Design Considerations
Freescale Semiconductor
40
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8126 device is designed into a system.
3.1
Start-up Sequencing Recommendations
Use the following guidelines for start-up and power-down sequences:
Assert
PORESET
and
TRST
before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN
can be held low or allowed to toggle during the beginning of the power-up sequence. However,
CLKIN
must
start toggling before the deassertion of
PORESET
and after both power supplies have reached nominal voltage levels.
If possible, bring up
V
DD
/
V
CCSYN
and
V
DDH
together. If it is not possible, raise
V
DD
/
V
CCSYN
first and then bring up
V
DDH
.
V
DDH
should not exceed
V
DD
/
V
CCSYN
until
V
DD
/
V
CCSYN
reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with
V
DDH
going down first and
then
V
DD
/
V
CCSYN
.
Note:
This recommended power sequencing for the MSC8126 is different from the MSC8102. See
Section 2.5.2
for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply
V
DDH
by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if V
DD
rises before V
DDH
(see
Figure 6
), current can pass from the V
DD
supply through the
device ESD protection circuits to the V
DDH
supply. The ESD protection diode can allow this to occur when V
DD
exceeds V
DDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
Never allow V
DD
to exceed V
DDH
+ 0.8V.
Design the V
DDH
supply to prevent reverse current flow by adding a minimum 10
Ω
resistor to GND to limit the
current. Such a design yields an initial V
DDH
level of V
DD
– 0.8 V before it is enabled.
After power-up,
V
DDH
must not exceed
V
DD
/
V
CCSYN
by more than 2.6 V.
3.2
Power Supply Design Considerations
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in
Migrating Designs from the MSC8102 to the MSC8122
(AN2716) and the
MSC8126 Design Checklist
(AN3374
for optimal system performance.
MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples
(AN2937)
provides detailed design information. See
Section 2.5.2
for start-up timing specifications.
Figure 33
shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MSC8126_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor |
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