參數(shù)資料
型號(hào)： MSC8122TVT6400
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 18/88頁(yè)
文件大?。?/td> 983K
代理商： MSC8122TVT6400
MSC8122 Technical Data, Rev. 13
1-8
Freescale Semiconductor
Signals/Connections
HD60
D60
ETHCOL
Reserved
Input/ Output
Input/ Output
Input/ Output
Input
Host Data Bus 60
Bit 60 of the DSI data bus.
System Bus Data 60
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
Ethernet Collision
In MII mode only, indicates that a collision was detected.
In RMII mode, this pin is reserved and can be left unconnected.
HD[61–63
]
D[61–63]
Reserved
Input/ Output
Input/ Output
Input
Host Data Bus 61–63
Bits 61–63 of the DSI data bus.
System Bus Data 61–63
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
HCID[0–2]
Input
Host Chip ID 0–2
With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]
matches the Chip_ID, or if HBCS is asserted.
HCID3
HA8
Input
Input
Host Chip ID 3
With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]
matches the Chip_ID, or if HBCS is asserted.
Host Bus Address 8
Used by an external host to access the internal address space.
HA[11–29]
Input
Host Bus Address 11–29
Used by external host to access the internal address space.
HWBS[0–3]
HDBS[0–3]
HWBE[0–3]
HDBE[0–3]
Input
Input
Input
Input
Host Write Byte Strobes
(In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
Host Data Byte Strobe
(in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable
(In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host read or write accesses.
Host Data Byte Enable
(in Synchronous single mode)
One bit per byte is used as a strobe enable for host write accesses
Table 1-5.
DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
Type
Description
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