參數(shù)資料
型號: MSC8122MP8000
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: Quad Core 16-Bit Digital Signal Processor
中文描述: 四核16位數(shù)字信號處理器
文件頁數(shù): 20/88頁
文件大?。?/td> 983K
代理商: MSC8122MP8000
MSC8122 Technical Data, Rev. 13
1-10
Freescale Semiconductor
Signals/Connections
TT1
Input/ Output
Bus Transfer Type 1
The bus master drives this pins during the address tenure to specify the type of the transaction. Some
applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101
and
vice
versa
. In these applications, TT1 functions as read/write signal.
TT[2–4]
CS[5–7]
Input/ Output
Output
Bus Transfer Type 2–4
The bus master drives these pins during the address tenure to specify the type of the transaction.
Chip Select 5–7
Enables specific memory devices or peripherals connected to the system bus.
CS[0–4]
Output
Chip Select 0–4
Enables specific memory devices or peripherals connected to the system bus.
TSZ[0–3]
Input/ Output
Transfer Size 0–3
The bus master drives these pins with a value indicating the number of bytes transferred in the current
transaction.
TBST
Input/ Output
Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers
eight words).
Interrupt Request 1
1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
IRQ1
GBL
Input
Output
Global
1
When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin
indicates that the transfer is global and should be snooped by caches in the system.
Interrupt Request 3
1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
IRQ3
BADDR31
Input
Output
Burst Address 31
1
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Interrupt Request 2
1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
IRQ2
BADDR30
Input
Output
Burst Address 30
1
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Interrupt Request 5
1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
IRQ5
BADDR29
Input
Output
Bus Burst Address 29
1
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
BADDR28
Output
Burst Address 28
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
BADDR27
Output
Burst Address 27
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Table 1-5.
DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
Type
Description
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MSC8122TMP6400V 功能描述:DSP 16BIT 400MHZ MULTI 431FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:StarCore 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA(20x20) 包裝:托盤
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