參數(shù)資料
型號(hào)： MSC8122_07
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Digital Signal Processor
中文描述： 四路數(shù)字信號(hào)處理器
文件頁數(shù)： 16/48頁
文件大?。?/td> 793K
代理商： MSC8122_07
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freescale Semiconductor
16
2.5
AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50
Ω
transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
Output Buffer Impedances
2.5.2
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power.
Section 2.5.3
describes the clocking characteristics.
Section 2.5.4
describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8122 device:
PORESET
and
TRST
must be asserted externally for the duration of the power-up sequence. See
Table 11
for timing.
If possible, bring up the
V
DD
and
V
DDH
levels together. For designs with separate power supplies, bring up the
V
DD
levels and then the
V
DDH
levels (see
Figure 7
).
CLKIN
should start toggling at least 16 cycles (starting after
V
DDH
reaches its nominal level) before
PORESET
deassertion to guarantee correct device operation (see
Figure 6
and
Figure 7
).
CLKIN
must not be pulled high during
V
DDH
power-up.
CLKIN
can toggle during this period.
Note:
See
Section 3.1
for start-up sequencing recommendations and
Section 3.2
for power supply design
recommendations.
The following figures show acceptable start-up sequence examples.
Figure 6
shows a sequence in which
V
DD
and
V
DDH
are
raised together.
Figure 7
shows a sequence in which
V
DDH
is raised after
V
DD
and
CLKIN
begins to toggle as
V
DDH
rises.
Figure 5. Overshoot/Undershoot Voltage for V
IH
and V
IL
Table 6. Output Buffer Impedances
Output Buffers
Typical Impedance (
Ω
)
System bus
Memory controller
Parallel I/O
Note:
50
50
50
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
GND
GND – 0.3 V
GND – 0.7 V
V
IL
V
IH
Must not exceed 10% of clock period
V
DDH
+ 17%
V
DDH
+ 8%
V
DDH
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