參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 28/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
2-4
AC Timings
2.6.2 Clock and Timing Signals
The following sections include a description of clock signal characteristics.
Table 2-5 shows the maximum frequency values for internal (Core, Reference, Bus, and DSI) and
external (CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded.
Table 2-5. Maximum Frequencies
Characteristic
Maximum in MHz
Core Frequency
250/275
Reference Frequency (REFCLK)
83.3/91.7
Internal Bus Frequency (BLCK)
83.3/91.7
DSI Clock Frequency (HCLKIN)
if REFCLK
≤ 70 MHz, HCLKIN = CLKOUT
if REFCLK > 70 MHz, HCLKIN = 70 MHz
External Clock Output Frequency (CLKOUT)
83.3/91.7
Note:
The REFCLK is CLKOUT.
Table 2-6. Clock Frequencies
Characteristics
Symbol
250 MHz Device
275 MHz Device
Min
Max
Min
Max
CLKIN frequency
FCLKIN
33 MHz
75 MHz
33 MHz
75 MHz
DLLIN frequency
FDLLIN
33 MHz
75 MHz
33 MHz
75 MHz
BCLK frequency
FBCLK
33 MHz
75 MHz
33 MHz
75 MHz
Reference Clock (REFCLK) frequency
FREFCLK
33 MHz
83.3 MHz
33 MHz
91.7 MHz
Output Clock (CLKOUT) frequency
FCLKOUT
33 MHz
83.3 MHz
33 MHz
91.7 MHz
SC140 core clock frequency
FCORE
165 MHz
250 MHz
165 MHz
275 MHz
Note:
The rise and fall time of external clocks should be 5 ns maximum
Table 2-7. System Clock Parameters
Characteristic
Minimum
Maximum
Unit
Phase jitter between BCLK and DLLIN
—
0.5
ns
CLKIN frequency
33
75
MHz
CLKIN slope
—
5
ns
DLLIN slope
—
2
ns
CLKOUT frequency jitter
1
—
(0.01
× F
CLKOUT) + FCLKIN jitter
MHz
CLKOUT phase jitter (in DLLOFF mode)2
—2
ns
Delay between CLKOUT and DLLIN3
—5
ns
Notes:
1.
Low CLKIN frequency causes poor PLL performance. Choose a FCLKIN value high enough to keep
the frequency after predivider (SPLLMFCLK) higher than 16.5 MHz
2.
Peak-to-peak.
3.
Not tested. Guaranteed by design.
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