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參數(shù)資料
| 型號(hào)： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 20/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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1-19
GPIO, TDM, UART, and Timer Signals
GPIO20
TDM1RDAT
Input/
Output
Input/
Output
General-Purpose Input Output 20
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two
dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing
model.
TDM1 Serial Receiver Data
The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for
TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter
describing TDM operation.
GPIO21
TDM0TSYN
Input/
Output
Input/
Output
General-Purpose Input Output 21
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two
dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing
model.
TDM0 Transmit frame Sync
Transmit Frame Sync for TDM 0.
GPIO22
TDM0TCLK
DONE2
DRACK2
Input/
Output
Input
Input/
Output
General-Purpose Input Output 22
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two
dedicated outputs.For details, refer to the MSC8102 Reference Manual GPIO programing
model.
TDM 0 Transmit Clock
Transmit Clock for TDM 0.
DMA Done 2
Signifies that the channel must be terminated. If the DMA generates DONE, the channel
handling this peripheral is inactive. As an input to the DMA, DONE closes the channel
much like a normal channel closing.
Note:
See the MSC8102 Reference Manual chapters on DMA and GPIO for
information on configuring the DRACK or DONE mode and pin direction.
DMA Data Request Acknowledge 2
Asserted by the DMA controller to indicate that the DMA controller has sampled the
peripheral request.
GPIO23
TDM0TDAT
IRQ13
Input/
Output
Input/
Output
Input
General-Purpose Input Output 23
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two
dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing
model.
TDM0 Serial Transmitter Data
The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for
TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter
describing TDM operation.
Interrupt Request 13
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
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| MSC8122TVT6400 | 32-BIT, 400 MHz, OTHER DSP, PBGA431 |
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| MSC8144ETVT800B | 133 MHz, OTHER DSP, PBGA783 |
| MSC8144EVT1000A | 133 MHz, OTHER DSP, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8102M4400 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8102RM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8102UG | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8103 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8103/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
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