- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359222 > MSC8101M1375F (MOTOROLA INC) Network Digital Signal Processor PDF資料下載
參數(shù)資料
| 型號： | MSC8101M1375F |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Network Digital Signal Processor |
| 中文描述： | 64-BIT, 68.75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 378K |
| 代理商： | MSC8101M1375F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5
20
Freescale Semiconductor
CPM73
SI RAM Corruption
Date Added:
8/5/2001
Description:
(7049)An access to the SI RAM bank from the 60x bus while the corresponding
TDM is active may result in data corruption within the SI RAM.
Workaround:
Associate the SI RAM bank with an inactive TDM before attempting to access
it. Once the accesses has been made, the SI RAM bank should be re-assigned to the active TDM.
System Number:
7049
Fix Plan:
Rev A
0K40A
CPM74
FCC HDLC Controller Stops Transmitting When Using Nibble Mode With MFF=0
Date Added:
8/27/2001
Description:
When running an FCC in HDLC nibble mode with the multi-frame per FIFO bit off
(MFF=0) the CPM may lose synchronization with the FCC HDLC controller. As a result the
HDLC controller will get stuck and stop transmission.
Workaround:
When running the FCC in HDLC nibble mode set the MFF=1 or alternatively run
the FCC in HDLC bit mode.
Fix Plan:
RevA
0K40A
CPM76
First transmitted bit zero in FCC Transparent Mode with GFMR[CTSS]=1
Date Added:
8/27/2001
Description:
When using an FCC in transparent mode the first bit of a frame is transmitted as
zero every time RTS is asserted before CTS is asserted when CTS is sampled synchronously with
data (GFMR[CTSS]=1). If CTS is in pulse mode (GFMR[CTSP]=1) only the first frame is affect-
ed because CTS is ignored thereafter. If CTS is not in pulse mode (GFMR[CTSP]=0) then every
frame is affected separately.
Workaround:
If the receiver synchronizes on a 8/16-bit sync pattern stored in the FDSR register
(GFMR[SYNL]=1x) ensure that the synchronization pattern starts with a “0”. If no synchroniza-
tion pattern is used (GRMR[SYNL]=0x) add a one-byte dummy buffer before sending the real
data buffers.
Fix Plan:
RevA
0K40A
CPM79
FCC Fast Ethernet Flow Control
Date Added:
3/14/2002
Description:
When the FCC receives a flow control pause message with MAC parameter
=0xffff, it sets a zero delay instead of maximum delay.
Fix Plan:
RevA
0K40A
CPM80
MCC CES User Template
Date Added:
3/14/2002
Description:
If the transparent MCC Tx CES channel requires the user template
(CHAMR[UTM]=1) only the first 8 bytes of the user defined pattern are transmitted. Then the
transmitter will continue to send bytes 4-7 of the pattern continuously until the counter reaches 0.
Any bytes defined in the pattern after byte 7 are never transmitted.
Workaround:
Use a template size of 8 bytes.
Fix Plan:
RevA
0K40A
CPM85
Only One BSY Interrupt Generated for AAL0
Date Added:
5/21/2002
Description:
When using AAL0, only one BSY interrupt will be received regardless of the num-
ber of BSY events that are generated.
Workaround:
None.
Fix Plan:
RevA
0K40A
Table 2.
Silicon Errata (Continued)
Errata
Number
Errata Description
Applies
to Mask
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC8101M1500F | Network Digital Signal Processor |
| MSC8101M1250F | Network Digital Signal Processor |
| MSC8101 | Network Digital Signal Processor |
| MSC8122_07 | Quad Digital Signal Processor |
| MSC8122 | Quad Core 16-Bit Digital Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8101M1500F | 功能描述:DSP 16BIT 300MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101UG/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8101VT1250F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC8101VT1375F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC8101VT1500F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。