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參數(shù)資料
| 型號： | MSC8101 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Silicon Errata for the MSC8101 Processor, Mask 0K40A |
| 中文描述： | 芯片勘誤表的MSC8101處理器，面具0K40A |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 378K |
| 代理商： | MSC8101 |
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Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5
Freescale Semiconductor
5
QSIU9
PowerPC Bus Speed Limited to 50MHz
Date Added:
10/5/2000:
Description:
The PPC Bus and Local Bus are limited to 50 MHz operation.
Workaround:
None. With Rev0 silicon, it is recommended to use 1:2.5:5 clock ratio
(Bus:CPM:Core) which will yield 125 MHz CPM and 250 MHz core when the bus clock frequen-
cy is set to 50 MHz.
System Number:
6355
Rev 0.1
0K40A
QSIU10
Spurious TEA Following Consecutive DPRAM, Register File Accesses
Date Added:
1/28/2001
Description:
An access to the DPRAM followed immediately by a write to the SIU register file
may result in a spurious TEA. The write to the SIU register file is successful despite the TEA.
Workaround:
None.
System Number:
6908
Fix Plan:
Rev 0.1
0K40A
QSIU11
Loss of Data Integrity Caused By Excessive PLL Jitter
Date Added:
1/28/2001
Description:
Excessive PLL jitter may cause loss of data integrity for accesses that cross the
Extended Core/Bus clock domain boundary in certain MODCK configurations.
Minimize PLL power supply noise and use clock configurations that result in input
clocks to both PLLs in the range of 20MHz-25MHz. For example, MODCK #40,
BUS:CPM:CORE = 1:2.5:5, with a 20MHz CLKIN which results in Bus = 48MHz, CPM
= 120MHz, Core = 240MHz.
System Number:
6915
Fix Plan:
Rev 0.1
0K40A
QSIU13
Software Watchdog Cannot be Enabled after Boot from Host
Date Added:
8/5/2001
Description:
The software watchdog is disabled when booting from host. It cannot be subse-
quently enabled because the SYPCR can only be written once.
Workaround:
None
Fix Plan:
Rev A
0K40A
QSIU15
60x Compatible Global Transaction Fail on RETRY
Date Added:
5/30/2000, modified 10/15/2002
Description:
Data may be lost on RETRY when global transactions are performed in 60x com-
patible mode.
Workaround:
When global transactions are used, 60x compatible mode cannot be used.
System Number:
5678
Fix Plan:
RevA
0K40A
Table 2.
Silicon Errata (Continued)
Errata
Number
Errata Description
Applies
to Mask
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| MSC8101M1375F | Network Digital Signal Processor |
| MSC8101M1500F | Network Digital Signal Processor |
| MSC8101M1250F | Network Digital Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC81010 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS |
| MSC8101M1250C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Network Digital Signal Processor |
| MSC8101M1250F | 功能描述:DSP 16BIT 250MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101M1375C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Network Digital Signal Processor |
| MSC8101M1375F | 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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