參數(shù)資料
型號(hào)： MSC8101
廠(chǎng)商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Silicon Errata for the MSC8101 Processor, Mask 0K40A
中文描述： 芯片勘誤表的MSC8101處理器，面具0K40A
文件頁(yè)數(shù)： 23/28頁(yè)
文件大小： 378K
代理商： MSC8101
Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5
Freescale Semiconductor
23
CPM101
FCC RxClav Timing Violation (Slave)
Date Added:
1/15/2004
Date Revised:
11/05/2004
Description:
FCC ATM Receive UTOPIA slave mode. When the RxFIFO is full, RxClav is ne-
gated 2 cycles before the end of the cell transfer, instead of 4. A master that polls RxClav or pauses
3 or 4 cycles before the end of the cell transfer may sample a false RxClav, and an overrun con-
dition may occur. The dashed line in the timing diagram below depicts the actual RxClav negation
(two cycles before the end of the cell transfer instead of four cycles). The signals in the timing
diagram are with respect to the master, so the Tx interface is shown.
Workaround:
1.
The master should not poll RxClav or pause a cell transfer 4 cycles before the end of a cell
transfer. The master should poll 2 cycles before the end of the current cell or later. This can
be achieved by introducing cell-to-cell polling (and transfer) delay, which is equal or larger
than one cell transfer time. If this can be achieved, the impact on performance is minimal.
2.
Configuring ATM only on FCC1 and setting FPSMR[TPRI] ensures the highest priority to
FCC1 Rx. In addition, for CPM usage lower then 80 percent (as reported by the CPM per-
formance tool based on UTOPIA maximal bus rate), the CPM performance is enough to
guarantee that the RxFIFO does not fill up.
0K40A
CPM110
FCC1 Prioritization
Date Added:
12/19/2003
Description:
The FCC1 receiver in Ethernet, HDLC, or Transparent controller mode is not ele-
vated to emergency status (priority 4 in Table 19-2 of the Reference Manual, "Peripheral Priori-
tization"), which may lead to a FIFO overrun if the system is heavily loaded (FCC1 receiver has
the highest priority excluding emergency status of other peripherals)
.
Workaround:
When allocating FCCs, assign FCC2 and FCC3 for Ethernet, HDLC or Transpar-
ent before FCC1, or assign FCC1 to the lowest bit rate interface. If FCC1 is allocated for ATM
and requires higher CPM usage than the other FCCs, disable its emergency status.
System Number:
11062
Fix Plan:
0K40A
Table 2.
Silicon Errata (Continued)
Errata
Number
Errata Description
Applies
to Mask
TxClk
TxEnb
TxClav
TxData
TxSOC
1
2
3
4
50
52
53
54
55
56
57
58
51
5
Clock cycles from end of cell:
4
3
2
1
X
H
H2
P44 P45 P46
X
X
P47 P48
x
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