參數(shù)資料
型號: MSC7115VF1000
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 266 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, BGA-400
文件頁數(shù): 17/56頁
文件大小: 1820K
代理商: MSC7115VF1000
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Specifications
Freescale Semiconductor
24
2.5.4
DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1
DDR DRAM Input AC Timing Specifications
Table 18 provides the input AC timing specifications for the DDR DRAM interface.
Figure 4. Timing Diagram for a Reset Configuration Write
Table 18. DDR DRAM Input AC Timing
No.
Parameter
Symbol
Min
Max
Unit
Mask Set
1L44X
Mask Set
1M88B
AC input low voltage
VIL
—VREF – 0.31
VREF – 0.31
V
AC input high voltage
VIH
VREF + 0.31
VDDM + 0.3
V
201
Maximum Dn input setup skew relative to DQSn
input
1026
900
ps
202
Maximum Dn input hold skew relative to DQSn
input
386
900
ps
Notes:
1.
Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0
≤ n ≤ 7).
2.
See Table 19 for tCK value.
3.
Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
Figure 5. DDR DRAM Input Timing Diagram
PORESET
Internal
HRESET
Input
Output(I/O)
Configuration Pins
are sampled
2
1
Dn
DQSn
D1
D0
201
202
201
Note: DQS centering is done internally.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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