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參數(shù)資料
| 型號(hào)： | MSC7115VF1000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 266 MHz, OTHER DSP, PBGA400 |
| 封裝： | 17 X 17 MM, BGA-400 |
| 文件頁數(shù)： | 14/56頁 |
| 文件大?。?/td> | 1820K |
| 代理商： | MSC7115VF1000 |
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Specifications
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
21
2.5.2.1
PLL Multiplier Restrictions
There are two restrictions for correct usage of the PLL block:
The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10.5–19.5 MHz.
The output frequency of the PLL multiplier must be in the range 300-600 MHz.
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet
these constraints.
2.5.2.2
Division Factors and Corresponding CLKIN Frequency Range
2.5.2.3
Multiplication Factor Range
The multiplier block output frequency ranges depend on the input clock frequency as shown in Table 11.
2.5.2.4
Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripheral depends on the value of the CLKCTRL[RNG] bit as shown
in Table 12.
This bit along with the CKSEL determines the frequency range of the core clock.
Table 10. CLKIN Frequency Ranges by Divide Factor Value
PLLDVF
Field Value
Divide
Factor
CLKIN Frequency Range
Comments
0x00
1
10.5 to 19.5 MHz
Pre-Division by 1
0x01
2
21 to 39 MHz
Pre-Division by 2
0x02
3
31.5 to 58.5 MHz
Pre-Division by 3
0x03
4
42 to 78 MHz
Pre-Division by 4
0x04
5
52.5 to 97.5 MHz
Pre-Division by 5
0x05
6
63 to 100 MHz
Pre-Division by 6
0x06
7
73.5 to 100 MHz
Pre-Division by 7
0x07
8
84 to 100 MHz
Pre-Division by 8
0x08
9
94.5 to 100 MHz
Pre-Division by 9
Note:
The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–9.
Table 11. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
Minimum PLLMLTF Value
Maximum PLLMLTF Value
300
≤ [Pre-Divided Clock × (PLLMLTF + 1)] ≤ 600 MHz
300/Pre-Divided Clock
600/Pre-Divided Clock
Note:
This table results from the allowed range for FLoop. The minimum and maximum multiplication factors are dependent on the
frequency of the Pre-Divided Clock.
Table 12. Fvco Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of Fvco
1
300
≤ Fvco ≤ 600 MHz
0
150
≤ Fvco ≤ 300 MHz
Note:
This table results from the allowed range for Fvco, which is FLoop modified by CLKCTRL[RNG].
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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