參數(shù)資料
型號(hào): MSC7110
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Low-Cost 16-Bit DSP with DDR Controller
中文描述: 低成本16位數(shù)字信號(hào)處理器與DDR控制器
文件頁數(shù): 4/8頁
文件大?。?/td> 97K
代理商: MSC7110
MSC7110 Product Brief, Rev. 2
4
Freescale Semiconductor
Features
I
2
C Port
2-wire serial interface through GPIO.
Filtered inputs for noise suppression.
Compatibility with I
2
C bus standard up to 100 kbps for standard mode and up to 400 kbps for
Fast mode.
Bidirectional Data Transfer Protocol.
Multiple-master operation that also allows any number of devices implementing the I
2
C-
master software module to access the memory simultaneously at boot or any time.
Compatible with the I
2
C-serial EEPROM access protocol, allowing memory access of up to
one MB.
General-Purpose I/O
(GPIO) Port
Bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.
Each port can be programmed separately to serve up to two dedicated peripherals.
Programmable Interrupt
Controller (PIC)
Consolidates maskable interrupt and non-maskable interrupt sources.
System Control
Reset controller.
Clock controller module.
Hardware bus monitors for the MSC7110 buses.
Software watchdog timer function.
fieldBIST hardware health diagnostics that can be invoked at power-up or off-line via
software.
Event port.
Internal PLL
Generates up to 266 MHz clock for the SC1400 core and up to 133 MHz for the crossbar
switch, DMA channels, M2 memory, and other peripherals.
Clock Synthesis Module
Programmable low-power Stop and Wait modes.
Generation of all device clocks.
Halt and restart capability for on-chip peripherals.
Reduced Power
Dissipation
Separate power supply for internal logic and I/O.
Typical case power consumption of 300–400 mW
Low-power standby modes.
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent).
fieldBIST Hardware
Diagnostics
Detects and provides visibility into unlikely field failures for systems with high availability. The
unique fieldBIST ensures that the device:
Has structural integrity.
Operates at the rated speed.
Is free from reliability defects.
Diagnostics can report partial or complete device inoperability. fieldBIST resolution can
pinpoint the following uniquely:
6 memory blocks, including ROM
3 logic levels (top, extended core, and peripherals)
1 PLL
Simple JTAG interface allows easy integration to system firmware.
Packaging
400 ball MAP-BGA.
17
×
17 mm.
0.8 mm pitch.
Pb-free or Pb-bearing spheres.
Table 1.
MSC7110 Features (Continued)
Feature
Description
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