參數(shù)資料
型號: MSC7110
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Low-Cost 16-Bit DSP with DDR Controller
中文描述: 低成本16位數(shù)字信號處理器與DDR控制器
文件頁數(shù): 2/8頁
文件大小: 97K
代理商: MSC7110
MSC7110 Product Brief, Rev. 2
2
Freescale Semiconductor
Features
Features
Table 1
lists the features of the Freescale MSC7110 device.
Table 1.
MSC7110 Features
Feature
Description
StarCore
SC1400 Core
Up to 1000 MMACS using an internal 266 MHz clock at 1.2 V. A multiply-accumulate
operation includes a multiply-add instruction with the associated data move and pointer
update.
4 data ALUs.
16 data registers, 40 bits each.
27 address registers, 32 bits each.
Hardware support for fractional and integer data types.
Very rich 16-bit wide orthogonal instruction set.
Up to six instructions executed in a single clock cycle.
Variable-length execution set (VLES) that can be optimized for code density and
performance.
JTAG port designed to comply with
IEEE
Std 1149.1.
On-chip emulator (OCE) module with real-time debugging capabilities.
Extended Core
The high performance extended core delivers up to 1000 MMACS using 4 ALUs running up to
266 MHz, including:
SC1400 core processor.
64 KB multi-port SRAM (M1) accessed by the SC1400 core with no wait states.
16 KB, 16-way instruction cache (ICache).
Programmable instruction fetch unit.
Write buffer (4-entry).
Extended core interface module.
Internal Memory
The large internal memory space totals 88 KB:
64 KB of M1 memory.
16 KB ICache.
8 KB boot ROM accessible from the SC1400 core.
External Memory
Interface
DDR memory controller.
Glueless interface to 133 MHz DDR-RAM (synchronous and half of internal clock).
14-bit external address bus supporting up to 1 GB.
16- or 32-bit external data bus.
Memory controller supports:
Byte enables for 32-bit external data bus.
Data pipeline to reduce data set-up time for synchronous devices.
Crossbar Switch
AHB-Lite crossbar switch, allowing up to four parallel data transfers between four master ports
and six slave ports, where each port connects to an AHB-Lite bus.
DMA Controller
Multi-channel DMA controller:
Up to 32 time-multiplexed channels.
Priority-based time-multiplexing between channels using 32 internal priority levels
Priorities can be fixed or round-robin.
A flexible channel configuration:
All channels support all features.
All channels connect to the slave ports on the crossbar.
External Interfaces
External interfaces and control modules managed on the advanced peripheral bus (APB)
including:
Time-division multiplexing (TDM) module supporting up to 128 channels.
Two 16-bit quad timers.
RS-232 interface/universal asynchronous receiver/transmitter (UART).
I
2
C interface.
Up to 37 general-purpose input/output (GPIO) signals.
Interrupt controller to handle external interrupt functions (input and output).
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