參數(shù)資料
型號(hào)： MSC220
廠商： Zarlink Semiconductor Inc.
英文描述： XpressFlow 2020 Ethernet Routing Switch Chipset
中文描述： XpressFlow 2020以太網(wǎng)路由交換機(jī)芯片組
文件頁(yè)數(shù)： 16/34頁(yè)
文件大?。?/td> 614K
代理商： MSC220
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XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1998
Vertex Networks, Inc.
15 Rev. 4.5 – February
1999
2.3
Management Bus Interface
t
Supports various industry standard micro-
processors including:
Intel 186/486 family or equivalent
Motorola MPC series embedded processors
t
Easily adapts to other industry standard CPUs
t
Provides separate Address and Data bus
t
Supports Big & Little Endian byte ordering
t
Supports 16- or 32-bit Data Bus
t
Provides a single interrupt signal to Switch
Manager CPU
2.3.1
Pin Description
Symbol
Type
Name & Functions
P_C[4:0]
CMOS Input
Processor Configuration bit [4:0]
: – During the Reset Cycle, the P_C[4:0] pins provides the proc-
essor configuration. By using external weak pull-up or -down resistors, they define the External
Management Bus Interface Configuration. These inputs are sampled at the trailing edge of the
Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Data Bus width – 16-bit or 32-bit
C[4] – Defines the timng relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
C[0]
C[1]
CPU Clock
Byte Order
Lo
1X Clock
Little Endian
Hi
2x Clock
Big Endian
C[2]
RWC
P_R/W#
P_W/R#
C[3]
C[4]
Bus Width
16-bit
32-bit
RDY Timng
Normal
Early
After RESET, these pins are used as
XpressFlow
Bus Data bit [31:27].
Address Bus Bit [11:1]
– I/O port address
P_A[11:1]
TTL In
(5VT)
TTL I/O-TS
(5VT)
TTL In
(5VT)
TTL In-
put (5VT)
P_D[15:0]
Data Bus Bit [15:0]
– a 16-bit synchronous data bus.
P_ADS#
Address Strobe
– indicates valid address is on the bus
P_RWC
Read/Write Control
– indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low
P_R/W#is used for PowerPC or other simlar processors.
C[1]=High
P_W/R#is used for 386, 486 or other simlar processors
Data Ready
– timng indicates for bus data valid
P_RDY#
TTL Out-
OD
TTL Out-OD
Bus Size 16
– response to bus master that the SC-201 only supports 16-bit data bus width.
TTL In
(5VT)
TTL Out-
put
chip configuration register
.
TTL In-ST
(5VT)
Switch Manager CPU (except 386)
CMOS
Output
CPU
TTL In
(5VT)
Output signal with programmable polarity.
P_BS16#
P_CS#
Chip Select
– indicates the
XpressFlow
Engine is the target for the current bus operation.
P_INT
Interrupt Request
to Switch Manager CPU
The polarity of this signal output is programmable via
P_RSTIN#
Power Up Reset Input
– Asynchronous Reset Input fromeither Power-Up Reset circuit or from
P_RSTOUT
Synchronous Reset Output
– Synchronous Reset Output for i386 famly as the Switch Manager
P_CLK
CPU Clock
– 1X Clock for the others
Note:
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