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參數(shù)資料
| 型號： | MSC220 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | XpressFlow 2020 Ethernet Routing Switch Chipset |
| 中文描述： | XpressFlow 2020以太網(wǎng)路由交換機(jī)芯片組 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 614K |
| 代理商： | MSC220 |
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XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1998
Vertex Networks, Inc.
11 Rev. 4.5 – February
1999
2
2.1 CAM Interface
FUNCTIONAL DESCRIPTION
t
Direct interface with MUSIC MU9C1480 1k x
64 bit Content Addressable Memory (CAM)
Expandable to support 8k MAC Addresses
t
Two access masters: HISC in
XpressFlow
Engine, and Switch Manager CPU
t
Master interface with CAM Interface logic via
two dedicated CAM Command Blocks
One for HISC
One for Switch Manager CPU
t
Both HISC and Switch Manager CPU can ac-
cess the CAM by setting up their corresponding CAM Command Blocks, and read the return informa-
tion from their own Response Data Block
2.1.1
Pin Description
Symbol
C_D[15:0]
Type
TTL
I/O-TS
CMOS
Output
Name & Functions
CAM Data Bus bit [15:0]
– a 16-bit data bus for Data/Command in-
put/output.
CAM Chip Enable
– Enables the CAM by registers the control signals
on its falling edge and release them on its rising edge. Also used for
locking and unlocking the cascaded daisy chain.
CAM Write Enable
– allows to write data or command to CAM
C_CE#
C_WE#
CMOS
Output
CMOS
Output
CMOS
Output
TTL
Input
TTL
Input
C_CM#
CAM Data/Command Select
– defines data or command operations
C_EC#
CAM Enable Comparison
– latches and enables the MF and FF outputs
during a comparison cycle.
CAM Match Flag
– indicates a valid match during a comparison cycle.
C_MF#
C_FF#
CAM Full Flag
– indicates there is no empty location in the CAM.
CAM
CAM
Interface
Logic
Command
Block
Response
Data Block
Command
Block
Response
Data Block
From HISC
To HISC
To CPU
From CPU
Block Diagram – CAM Interface
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