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參數(shù)資料
| 型號： | MS80C51C-30R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 13/132頁 |
| 文件大?。?/td> | 10886K |
| 代理商： | MS80C51C-30R |
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183
ATmega8535(L)
2502K–AVR–10/06
TWI Status Register – TWSR
Bits 7..3 – TWS: TWI Status
These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The dif-
ferent status codes are described later in this section. Note that the value read from
TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application
designer should mask the prescaler bits to zero when checking the status bits. This
makes status checking independent of prescaler setting. This approach is used in this
datasheet, unless otherwise noted.
Bit 2 – Res: Reserved bit
This bit is reserved and will always read as zero.
Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
To calculate bit rates, see “Bit Rate Generator Unit” on page 180. The value of
TWPS1..0 is used in the equation.
TWI Data Register – TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the
TWDR contains the last byte received. It is writable while the TWI is not in the process of
shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
Note that the Data Register cannot be initialized by the user before the first interrupt
occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted
out, data on the bus is simultaneously shifted in. TWDR always contains the last byte
present on the bus, except after a wake-up from a sleep mode by the TWI interrupt. In
this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no
data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled
automatically by the TWI logic, the CPU cannot access the ACK bit directly.
Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the Two-wire Serial Bus.
TWI (Slave) Address Register
– TWAR
Bit
7654
321
0
TWS7
TWS6
TWS5
TWS4
TWS3
–
TWPS1
TWPS0
TWSR
Read/Write
R
RRRR
R
R/W
Initial Value
1111
100
0
Table 74. TWI Bit Rate Prescaler
TWPS1
TWPS0
Prescaler Value
00
1
01
4
10
16
11
64
Bit
7654
321
0
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
TWDR
Read/Write
R/W
Initial Value
1111
111
1
Bit
7654
321
0
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
TWAR
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