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參數(shù)資料
| 型號： | MS62256H-35RC |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K x 8 HIGH SPEED CMOS STATIC RAM |
| 中文描述： | 32K的× 8高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 108K |
| 代理商： | MS62256H-35RC |
MOSEL-VITELIC
MS62256H
Switching Waveforms (Write Cycle)
WRITE CYCLE 2(1,6)
NOTES:
1.
W must be high during address transitions.
2.
The internal write time of the memory is defined by the overlap E active and W low. Both signals must be active to initiate and
any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3.
TWR is measured from the earlier of E or W going high at the end of write cycle.
4.
During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5.
If the E low transition occurs simultaneously with the W low transitions or after the W low transition, outputs remain in a high
impedance state.
6.
G is continuously low (G = VIL).
7.
DOUT is the same phase of write data of this write cycle.
8.
DOUT is the read data of next address.
9.
If E is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied to them.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1b on page 4. This parameter is guaran-
teed and not 100% tested.
11. tCW is measured from E going low to the end of write.
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