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參數(shù)資料
| 型號(hào)： | MS27C801 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit (1Mb x 8) UV EPROM and OTP EPROM |
| 中文描述： | 8兆（1兆× 8）紫外線存儲(chǔ)器和OTP存儲(chǔ)器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 158K |
| 代理商： | MS27C801 |
9/16
M27C801
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. This can
be achieved with STMicroelectronics M27C801
due to several design innovations to improve pro-
gramming efficiency and to provide adequate mar-
gin for reliability. Before starting the programming
the internal MARGIN MODE circuit is set in order
to guarantee that each cell is programmed with
enough margin. Then a sequence of 50μs pro-
gram pulses are applied to each byte until a cor-
rect verify occurs. No overprogram pulses are
applied since the verify in MARGIN MODE pro-
vides the necessary margin.
Program Inhibit
Programming of multiple M27C801s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including GV
PP
of the par-
allel M27C801 may be common. A TTL low level
pulse applied to a M27C801's E input, with V
PP
at
12.75V, will program that M27C801. A high level E
input inhibits the other M27C801s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V
IL
. Data should be verified with t
ELQV
after the
falling edge of E.
Figure 8. Programming Flowchart
AI01271B
n = 0
Last
Addr
VERIFY
E = 50
μ
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
SET MARGIN MODE
RESET MARGIN MODE
Figure 7. Programming and Verify Modes AC Waveforms
tAVEL
VALID
AI01270
A0-A19
Q0-Q7
VCC
DATA IN
DATA OUT
E
tQVEL
tVCHEL
tVPHEL
tEHQX
tEHVPX
tELQV
tELEH
tEHQZ
tVPLEL
PROGRAM
VERIFY
GVPP
tEHAX
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