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參數(shù)資料
| 型號： | MRFIC0919 |
| 廠商： | Motorola, Inc. |
| 英文描述： | RF Power Amplifiers(RF功率放大器) |
| 中文描述： | 射頻功率放大器（射頻功率放大器） |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 196K |
| 代理商： | MRFIC0919 |
MRFIC0919
9
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
level is needed for correct operation of the demoboard. The
following procedure will guaranty safe operation for doing the
RF measurements.
Note: make sure that Bias1 (Pin 8) is connected to ground
or will have equivalent potential for nominal biasing of Buffer
stage.
1. Apply RF input power (RF In) >3.0 dBm.
2. Apply VDB = 3.0 to 5.0 V.
3. Check that Vss reaches approximatively –5.1 V (settling of
the negative voltage).
4. Apply VD1,2&3 = 3.0 to 5.5 V.
5. Measure RF output power and relevant parameters.
Proceed in the reverse order to switch off the Power
Amplifier.
For linear operation, an external negative voltage will have
to be supplied to the VSS pin to maintain initial quiescent
operating conditions of the FET amplifiers since the RF input
will not provide sufficient voltage to operate the negative
voltage generator. When using an external negative voltage
supply, supply voltage to VDB (Pin 16) would no longer be
required.
Control Considerations
MRFIC0919 application uses the drain control technique
developed for our previous range of GaAs IPAs (refer to
application note AN1599). This method relies on the fact that
for an RF amplifier operating in satuaration mode, the RF
output power is proportional to the square of the Amplifier
drain voltage: Pout(Watt)=k*VD(Volt)*VD(Volt).
In the proposed application circuit (see Figure 2), a PMOS
FET is used to switch the IPA drain and vary the drain supply
voltage from 0 to battery voltage. As the PMOS FET has a
non linear behavior, an OpAmp is included in the application.
This OpAmp is linearizing the PMOS by sensing its drain
output and gives a true linear relationship between the
Control voltage and the RF output voltage.
The obtained power control transfer function is so linear
and repeatable than it can be used to predict the output
power within a dynamic range of 25 to 30 dB over frequency
and temperature. This so called “open–loop” arrangement
eliminates the need for coupler and detector required for the
classical but complex closed–loop control and consequently
reduces the Insertion Loss from Power Amplifier to the
Antenna.
The block diagram (Figure 16) shows the principle of
operation as implemented in the application circuit of
Figure 2. The OpAmp is connected as an inverter to
compensate the negative gain of the PMOS switch.
Figure 16. Drain Control through
PMOS Switch
Vbat
Gain Set
PA
Vramp
PMOS
Vdrain
RF Out
RF In
NOTE:
The positive voltage generated by the Buffer stage can
be used to supply the OpAmp and make it possible to
drive a NMOS switch as a voltage follower. Doing so,
the main advantage is to have a lower Rdson switch
and better intrinsic linearity.
The following plot illustrates the ”open–loop” performance
as far as temperature stability. The measured datas are
displayed in a log–scale in order to have a good
representation of both the dynamic and the linearity of
control. The variation of Pout accross the frequency band are
also very small (less than 1.0 dB ripple) and are kept to that
small amount when controlling Pout through the Drain
voltage.
40
–10
Po
VD (dBV)
Figure 17. Pout versus VD
35
30
25
20
15
10
5.0
–8.0
–6.0
–4.0
–2.0
0
2.0
4.0
6.0
8.0
25
°
C
–40
°
C
85
°
C
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