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參數(shù)資料
| 型號(hào)： | MRFIC0919 |
| 廠商： | Motorola, Inc. |
| 英文描述： | RF Power Amplifiers(RF功率放大器) |
| 中文描述： | 射頻功率放大器（射頻功率放大器） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 196K |
| 代理商： | MRFIC0919 |
MRFIC0919
8
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
APPLICATIONS INFORMATION
Design Philosophy
The MRFIC0919 is a high performance three stage GaAs
IPA (Integrated Power Amplifier) designed for GSM handheld
radios (880 to 915 MHz frequency band). With a 3.6 V battery
supply, it delivers typically 35.3 dBm of Output Power with
53% Power Added Efficiency.
It features an internal Negative Voltage Generator based
on RF rectification of the input carrier after its amplification by
a dedicated buffer stage (see Internal Block Diagram). This
method eliminates spurs found on the Output signal when
using DC/DC converter type negative voltage generators,
either on or off chip. The buffer also generates a step–up
positive voltage which can be used to drive a N–MOS drain
switch.
The RF input power is split internally to the 3 stage RF
line–up (Q1,Q2 andQ3) and the Buffer. This arrangement
allows separate operation of Voltage Generation and Power
Amplification for maximum flexibility.
External Circuit Considerations
The MRFIC0919 can be tuned by changing the values
and/or positions of the appropriate external components (see
Figure 1. Reference Circuit). While tuning the RF line–up, it is
recommended to apply external negative supply in order to
prevent any damage to the power amplifier stages. Poor
tuning on the input may not provide enough RF power to
operate the negative voltage generator properly.
Input matching is a shunt–C, series–L low–pass structure
and should be optimized at the rated RF Input power (e.g.,
3.0 dBm). Since the Input line feeds both 1st stage and
buffer, Input matching should be iterated with Buffer and Q1
drain matching. Note that a DC blocking capacitor is included
on chip.
Buffer drain is supplied and matched through a discrete
chip inductor. Its value is tuned to get the maximum output
from voltage generator.
The step–up positive voltage available at Pin 1 is both
decoupled and maximized by a small shunt capacitor. This
positive voltage which is approximately twice the buffer drain
voltage can be used to drive a N–MOS drain switch for best
performance.
Q1 drain is supplied and matched through a printed
microstrip line that could be replaced by a discrete chip
inductor as well. Its length (or equivalent inductor value) is
tuned by sliding the RF decoupling capacitor along to get the
maximum gain on the first stage. Make sure when laying out
the PCB to put enough ground pads and vias close to the
microstrip lines to help for this fine tuning.
Q2 is supplied through a printed microstrip line that
contributes also to the interstage matching in order to provide
optimum drive to the final stage. The line length is very small
so replacing it with a discrete inductor is not practical.
Q3 drain is fed via a printed line that must handle the high
supply current of that stage (2.0 to 3.0 Amp peak) without
significant voltage drop. This line can be buried in an inner
layer to save PCB space or be a discrete RF choke.
Output matching is accomplished with a two stage
low–pass network. Easy implementation is achieved with
shunt capacitors mounted along a 30
microstrip
transmission line. Value and position are chosen to reach a
load line of 1.8
while conjugating the device output
parasitics. The network must also properly terminate the
second and third harmonic to optimize efficiency and reduce
harmonic level. Use of high Q capacitor for the output
matching circuit is recommended in order to get the best
Output Power and Efficiency performance.
Biasing Considerations
The internally generated negative voltage is clamped by
an external Zener diode in order to eliminate variation linked
to Input power or Buffer supply. This negative voltage is used
by three independent bias circuits to set the proper quiescent
current of all stages. Each bias circuit is equivalent to a
current source sinking its value from the bias pin. When the
bias pins are grounded, nominal quiescent current and
operating point of each RF stage are selected.
Q1 and Buffer share the Bias1 (0.25 mA) while Q2 and Q3
have dedicated Bias2 (0.25 mA) and Bias3 (0.5 mA)
respectively. It is also possible to reference those bias pins to
higher voltage than Gnd by using a series resistor that drops
the equivalent voltage.
If those pins are left open, the corresponding stages are
pinched–off. Thus the bias pins can be used as a means to
select the MRFIC0919 or MRFIC1819 in a dual band
configuration. The MRFIC1819 is the partner device to the
MRFIC0919 and is designed for DCS1800/PCS1900
applications.
Table 2. Pin Function Description
Pin
Symbol
Description
1
VP
VD3
RF Out
Positive voltage output
2
Third stage drain supply
3
RF output
4
RF Out
RF output
5
RF Out
RF output
6
Bias3
Third stage bias
7
Bias2
Second stage bias
8
Bias1
Buffer and first stage bias
9
VSS
VSC
VD2
Gnd
Negative voltage output
10
Negative voltage check
11
Second stage drain supply
12
Tied to ground externally
13
VD1
RF In
First stage drain supply
14
RF input
15
Gnd
Tied to ground externally
16
VDB
Buffer stage drain supply
VSC is an open drain internal FET switch which is biased
through the negative voltage. Consequently, this pin is high
impedance when negative voltage is okay and low
impedance (about 40
) when negative voltage is missing.
Operation Procedure
The MRFIC0919 is a standard MESFET GaAs Power
Amplifier, presence of a negative voltage to bias the RF
line–up is essential in order to avoid any damage to the parts.
Due to the fact that the negative voltage is generated through
rectification of the RF input signal, a minimum input power
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相關(guān)代理商/技術(shù)參數(shù) |
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| MRFIC0931 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:BALANCED TRANSMIT MIXER SILICON MONOLITHIC INTEGRATED CIRCUIT |
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| MRFIC1501R2 | 制造商:Freescale Semiconductor 功能描述: |
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