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參數(shù)資料
| 型號： | MRF3010 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 功率晶體管 |
| 英文描述： | LATERAL N-CHANNEL BROADBAND RF POWER MOSFET |
| 中文描述： | L BAND, Si, N-CHANNEL, RF POWER, MOSFET |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 106K |
| 代理商： | MRF3010 |
MRF3010
2
MOTOROLA RF DEVICE DATA
ELECTRICAL CHARACTERISTICS – continued
(TC = 25
°
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = 10 V, ID = 50 mA)
VGS(th)
2
2.5
5
Vdc
Drain–Source On–Voltage
(VGS = 10 V, ID = 1 A)
VDS(on)
–
1.5
–
Vdc
Forward Transconductance
(VDS = 10 V, ID = 1 A)
gfs
0.35
0.55
–
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 28 V, VGS = 0, f = 1 MHz)
Ciss
–
15
–
pF
Output Capacitance
(VDS = 28 V, VGS = 0, f = 1 MHz)
Coss
–
9
–
pF
Reverse Transfer Capacitance
(VDS = 28 V, VGS = 0, f = 1 MHz)
Crss
–
0.7
–
pF
FUNCTIONAL CHARACTERISTICS
Common Source Power Gain
(VDD = 28 Vdc, Pout = 10 W, IDQ = 50 mA, f = 1.6 GHz)
Gps
9.5
10.5
–
dB
Drain Efficiency
(VDD = 28 Vdc, Pout = 10 W, IDQ = 50 mA, f = 1.6 GHz)
η
45
50
–
%
Output Mismatch Stress
(VDS = 28 Vdc, Pout = 10 W, IDQ = 50 mA, f = 1600 MHz,
Load VSWR 30:1 at All Phase Angles)
Ψ
No Degradation in Output Power
Series Equivalent Input Impedance
(VDD = 28 Vdc, Pout = 10 W, IDQ = 50 mA, f = 1.6 GHz)
Zin
–
3.1+j7.18
–
Series Equivalent Output Impedance
(VDD = 28 Vdc, Pout = 10 W, IDQ = 50 mA, f = 1.6 GHz)
Zol
–
6.16–j4.75
–
R2
R3
R4
Z1
Z2
Z3
Z4
Z5
Z6
220
, 1/4 W Resistor
10 k
, 2 W Resistor
10 k
, 1/8 W Resistor
0.081
′′
x 0.42
′′
Microstrip
0.081
′′
x 1.24
′′
Microstrip
0.32
′′
x 0.48
′′
Microstrip
0.35
′′
x 0.5
′′
Microstrip
0.15
′′
x 0.44
′′
Microstrip
0.081
′′
x 1.165
′′
Microstrip
C1, C6, C10, C12
C2, C3, C7, C8
C4, C11
C5, C9
C13
L1
L2
L3
R1
24 pF, “A” Chip Capacitor, ATC
0.8–8.0 pF, Variable Capacitor, Johansen Gigatrim
240 pF, “A” Chip Capacitor, ATC
0.1
μ
F, Ceramic Capacitor
50
μ
F, 50 V, Electrolytic Capacitor
Ferroxcube VK200–19/4B
2 Turns, 0.175
′′
ID, 20 AWG, Close Wound
10 Turns, 20 AWG, Close Wound
1 k
, 1/4 W Resistor
Figure 1. 1.6 GHz Test Circuit Schematic
RF
OUTPUT
C2
C1
VDD
INPUT
VGG
INPUT
Z1
L1
R1
C4
C5
C6
R2
C3
Z2
Z3
DUT
RF
INPUT
Z4
L2
C7
C8
Z5
C12
C9
C10
C11
+
C13
L3
R3
Z6
R4
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