參數(shù)資料
型號(hào)： MRF24J40
廠商： Microchip Technology Inc.
英文描述： IEEE 802.15.4⑩ 2.4 GHz RF Transceiver
中文描述： IEEE 802.15.4標(biāo)準(zhǔn)⑩2.4 GHz射頻收發(fā)器
文件頁(yè)數(shù)： 36/66頁(yè)
文件大小： 748K
代理商： MRF24J40
MRF24J40
DS39776A-page 34
Advance Information
2006 Microchip Technology Inc.
7.4.2
FREEING RECEIVE BUFFER SPACE
The RX buffer is cleared when the length byte of the
packet and the last byte of the FCS are read. Once both
of these values are read from the RX buffer, the buffer
will enable itself to receive another packet. Because
the LQI and RSSI values are appended to the end of
the packet after the FCS, it may be advisable to read
these values out of the RX buffer before reading the
FCS.
Alternatively, it is possible to clear the RX buffer by
flushing it. This is done through the RXFLUSH register.
7.5
Transceiver
The MRF24J40 receiver features a low IF architecture
and consists of an LNA, a pair of down conversion
mixers, polyphase channel filters, baseband limiter
amplifiers and RSSI technology. An ADC is used to
sample the RSSI value and the sampled data is stored
in a register from which the data can be read out via the
SPI bus. The local oscillator generation circuits (VCO,
PLL and buffers) are shared with the receiver and
transmitter. The Low Noise Amplifier (LNA) features a
differential input for high performance. The RX/TX
switch is integrated and LNA input and Power Amplifier
(PA) output share the same pins. A common external
matching network and single-ended to differential con-
version is required. The transmitter features a direct
conversion architecture and has a 0 to -38.75 dBm out-
put power. The output power adjustment is in 1.25 dB
step. The TX gain is programmed by the SPI bus.
REGISTER 7-3:
RXFLUSH: RECEIVE FIFO FLUSH REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
W-0
r
r
RXWRTBLK
CMDONLY
DATAONLY
BCNONLY
RXFLUSH
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-5
bit 4
Unimplemented:
Read as ‘
0
’
Reserved:
Maintain as ‘
0
’
RXWRTBLK:
Software Write to RX FIFO Address bit
1
= Writing to any RX FIFO address is enabled
0
= Writing to any RX FIFO address is disabled
CMDONLY:
Command Packet Receive bit
1
= Only command packets are received, all other packets are filtered out
0
= All valid packets are received
DATAONLY:
Data Packet Receive bit
1
= Only data packets are received, all other packets are filtered out
0
= All valid packets are received
BCNONLY:
Beacon Packet Receive bit
1
= Only beacon packets are received, all other packets are filtered out
0
= All valid packets are received
RXFLUSH:
Flush RX FIFO Address bit
1
= Flush the RX FIFO. Cleared by hardware.
0
=
Previous flush complete
bit 3
bit 2
bit 1
bit 0
相關(guān)PDF資料
PDF描述
MRF24J40-I IEEE 802.15.4⑩ 2.4 GHz RF Transceiver
MRF24J40-IMM IEEE 802.15.4⑩ 2.4 GHz RF Transceiver
MRSM75 Rotation detection MR sensor
MRUS51S Micro power Built-in IC ultra-minimum MR sensor
MS-012AA SOIC: 8−LEAD (POWER ICS ONLY)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MRF24J40_08 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:IEEE 802.15.4? 2.4 GHz RF Transceiver
MRF24J40_10 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:IEEE 802.15.4a?￠ 2.4 GHz RF Transceiver
MRF24J40-I 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:IEEE 802.15.4⑩ 2.4 GHz RF Transceiver
MRF24J40-I/ML 功能描述:射頻收發(fā)器 2.4 Ghz IEEE/ZigBee RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
MRF24J40-I/ML 制造商:Microchip Technology Inc 功能描述:ZIGBEE Transceiver IC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*