參數(shù)資料
    型號(hào): MRF24J40
    廠商: Microchip Technology Inc.
    英文描述: IEEE 802.15.4⑩ 2.4 GHz RF Transceiver
    中文描述: IEEE 802.15.4標(biāo)準(zhǔn)⑩2.4 GHz射頻收發(fā)器
    文件頁(yè)數(shù): 11/66頁(yè)
    文件大?。?/td> 748K
    代理商: MRF24J40
    2006 Microchip Technology Inc.
    Advance Information
    DS39776A-page 9
    MRF24J40
    3.0
    MEMORY ORGANIZATION
    All memory in the MRF24J40 is implemented as static
    RAM. There are five types of memory in the
    MRF24J40:
    Short Address Control Registers
    Long Address Control Registers
    Transmit Buffers
    Receive Buffers
    Security Buffer
    The control registers, both long and short, are used for
    configuration, control, and status retrieval of the
    MRF24J40. The control registers are directly read and
    written to by the SPI interface. The transmit and receive
    buffers contain transmit and receive memory used by
    the controller to transmit and receive data.
    The security buffer provides an engine for the
    MRF24J40 MAC, which is compatible with the
    IEEE 802.15.4 LR-WPAN (ZigBee). The security buffer
    contains the following features:
    Transmit encryption and receive decryption.
    Seven-mode security suite.
    64 x 8-bit security RAM for security suite storing;
    one receive key and three transmit keys for TX
    FIFOs. Beacon FIFO and GTS2 FIFO share the
    same key space since they will not conflict with
    each other. Normal FIFO and GTS1 FIFO both
    have their own transmit key.
    Security of APL and NWK layers can be achieved
    using the same engine. The upper layer security
    function is compliant to the ZigBee V1.0 and
    ZigBee 2006 specifications.
    The SPI interface used to write and read these regis-
    ters is described in
    Section 4.0 “Serial Peripheral
    Interface (SPI)”
    .
    Figure 3-1 shows the data memory organization for the
    MRF24J40.
    FIGURE 3-1:
    MRF24J40 MEMORY SPACE
    Short Address
    Control Registers
    TXB FIFO
    Long Address
    Control Registers
    Security Buffer
    RX FIFO
    TXN FIFO
    GTS1 FIFO
    GTS2 FIFO
    Transmit
    Buffers
    Control
    Registers
    Security
    Receive
    FIFO
    000h
    07Fh
    080h
    0FFh
    100h
    17Fh
    180h
    1FFh
    200h
    27Fh
    280h
    2BEh
    2BFh
    300h
    38Fh
    Long Address
    Space
    Short Address
    Space
    00h
    3Fh
    Unimplemented
    2FFh
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