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參數(shù)資料
| 型號(hào)： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 463K |
| 代理商： | MR82510 |
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M82510
20. GSRDGENERAL STATUS REGISTER
GSRDGeneral Status Register
271072–33
This register reflects all the pending block-level In-
terrupt requests. Each bit in GSR reflects the status
of a block and may be individually enabled by GER.
GER masks-out interrupts from GIR; it does not
have any effect on the bits in GSR. The only way
that the bits can be masked out in GSR (i.e., not
appear in GSR) is if they are masked out at the lower
level.
TIRDTimers Interrupt RequestD
This bit indicates
that one of the timers has expired. (See TMST)
TxIRDTransmit Machine Interrupt RequestD
In-
dicates that the Transmit Machine is either empty or
disabled (Idle).
MIRDModem Interrupt RequestD
This bit, if set,
indicates an interrupt from the Modem Module. (As
reflected in MODEM STATUS.)
RxIRDReceive Machine Interrupt RequestD
(As
reflected in RST.)
TFIRDTransmit
FIFO occupancy is below or equal to threshold.
FIFO
Interrupt
RequestD
Tx
RFIRDReceive FIFO Interrupt RequestD
Rx FIFO
Occupancy is above threshold.
21. GIR/BANKDGENERAL INTERRUPT REGISTER/BANK REGISTER
General Interrupt Register/Bank Register
271072–34
This register holds the highest priority enabled pend-
ing interrupt from GSR. In addition it holds a pointer
to the current register segment. Writing into this reg-
ister will update only the BANK bits.
BANK1, BANK0DBank Pointer BitsD
These two
bits point to the currently accessible register bank.
The user can read and write to these bits. The ad-
dress of this register is always two within all four
register banks.
BI2, BI1, BI0,DInterrupt Bits 0–2D
These three
bits reflect the highest priority enabled pending inter-
rupt from GSR.
101: Timer Interrupt (highest priority)
100: Tx Machine Interrupt
011: Rx Machine Interrupt
010: Rx FIFO Interrupt
001: Tx FIFO Interrupt
000: Modem Interrupt (lowest priority)
IPNDInterrupt PendingD
This bit is active low. It
indicates that there is an interrupt pending. The in-
terrupt logic asserts the INT pin as soon as this bit
goes active. (Note: the GIR register is continuously
updated; so that, while the user is serving one inter-
rupt source, a new interrupt with higher priority may
enter GIR and replace the older interrupt.)
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR8251A | PROGRAMMABLE COMMUNICATION INTERFACE |
| MR851G | Axial Lead Fast Recovery Rectifiers |
| MR851RL | Axial Lead Fast Recovery Rectifiers |
| MR851RLG | Axial Lead Fast Recovery Rectifiers |
| MR852G | Axial Lead Fast Recovery Rectifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR82510/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8251A | 制造商:Intel 功能描述: |
| MR8251A/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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