參數(shù)資料
型號(hào): MR82510
廠商: Intel Corp.
英文描述: ASYNCHRONOUS SERIAL CONTROLLER
中文描述: 異步串行控制器
文件頁(yè)數(shù): 26/40頁(yè)
文件大?。?/td> 463K
代理商: MR82510
M82510
18. TMIEDTIMER INTERRUPT ENABLE REGISTER
TMIEDTimers/Interrupt Enable Register
271072–31
This is the enable register for the Timer Block. It is
used to mask out interrupt requests generated by
the status bits of the TMST register.
TBIEDTimer B Expired Interrupt EnableD
En-
ables Interrupt on TBEx bit of TMST.
TAIEDTimer A Expired Interrupt EnableD
En-
ables Interrupt on TAEx bit of TMST.
19. MIEDMODEM INTERRUPT ENABLE REGISTER
MIEDModem Interrupt Enable Register
271072–32
This register enables interrupts from the Modem
Block. It is used to mask out interrupt requests gen-
erated by the status bits of the MODEM STATUS
register.
DCDEDDelta DCD Interrupt EnableD
Enables In-
terrupt on DDCD bit of MODEM STATUS.
RIEDDelta RI Interrupt EnableD
Enables Interrupt
on DRI bit of MODEM STATUS.
DSREDDelta DSR Interrupt EnableD
Enables In-
terrupt on DSR bit of MODEM STATUS.
CTSEDDelta CTS Interrupt EnableD
Enables In-
terrupt on DCTS bits of MODEM STATUS.
STATUS/INTERRUPT
The M82510 has two device status registers, which
reflect the overall status of the device, and five block
status registers. The two device status registers,
GSR and GIR, and supplementary in function. GSR
reflects the interrupt status of all blocks, whereas
GIR depicts the highest priority interrupt only. GIR is
updated after the GSR register; the delay is of ap-
proximately two clock cycles.
26
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MR82510/B 制造商:Rochester Electronics LLC 功能描述:
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