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參數(shù)資料
| 型號： | UPD44325084F5-E50-EQ2-A |
| 元件分類： | SRAM |
| 英文描述： | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大小： | 387K |
| 代理商： | UPD44325084F5-E50-EQ2-A |
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14
Data Sheet
M16784EJ4V0DS
μPD44325084, 44325094, 44325184, 44325364
Truth Table
Operation
CLK
R#
W#
D or Q
WRITE cycle
L
→ H
H
L
Data in
Load address, input write data on two
Input data
DA(A+0)
DA(A+1)
DA(A+2)
DA(A+3)
consecutive K and K# rising edge
Input clock
K(t+1)
↑
K#(t+1)
↑
K(t+2)
↑
K#(t+2)
↑
READ cycle
L
→ H
L
X
Data out
Load address, read data on two
Output data
QA(A+0)
QA(A+1)
QA(A+2)
QA(A+3)
consecutive C and C# rising edge
Output clock
C#(t+1)
↑
C(t+2)
↑
C#(t+2)
↑
C(t+3)
↑
NOP (No operation)
L
→ H
H
D = X, Q = High-Z
Clock stop
Stopped
X
Previous state
Remarks 1. H : HIGH, L : LOW,
× : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then data outputs are delivered at K and K# rising edges.
3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at
the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
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參數(shù)描述 |
|---|---|
| UPD44325092BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44325094BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325094BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325182BF5-E33-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述: |
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