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參數(shù)資料
| 型號(hào)： | MR80C52CXXX-12SCR |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 152/198頁(yè) |
| 文件大?。?/td> | 4822K |
| 代理商： | MR80C52CXXX-12SCR |
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57
8111C–MCU Wireless–09/09
AT86RF231
Only second level filter rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, are applied to
the received frame.
Table 7-8 on page 57 shows the typical configuration of a device operating promiscuous mode.
If the radio transceiver is in promiscuous mode, second level of filtering according to
IEEE 802.15.4-2006, section 7.5.6.2, is applied to a received frame. However, an IRQ_3
(TRX_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit
RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the
reception of a frame with a valid FCS.
If a device, operating in promiscuous mode, receives a frame with a valid FCS which further
passed the third level of filtering according to IEEE 802.15.4-2006, section 7.5.6.2, an acknowl-
edgement frame would be transmitted. According to the definition of the promiscuous mode a
received frame shall not be acknowledged, even if it is requested. Thus register bit
AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set to 1.
In all receive modes an IRQ_5 (AMI) interrupt is issued, when the received frame matches the
node's address according to the filter rules described in Section 7.2.3.5 “Frame Filtering” on
Alternatively, in Basic Operating Mode RX_ON state, when a valid PHR is detected, an IRQ_2
(RX_START) is generated and the frame is received. The end of the frame reception is signal-
ized with an IRQ_3 (TRX_END). At the same time the register bit RX_CRC_VALID (register
0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2 “Frame Check
Sequence (FCS)” on page 85). According to the promiscuous mode definition the
RX_CRC_VALID bit needs to be checked in order to dismiss corrupted frames.
Table 7-8.
Configuration of Promiscuous Mode
Register
Register Name
Description
Address
Bits
0x20,0x21
0x22,0x23
0x24,
...
0x2B
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
...
IEEE_ADDR_7
Address shall be set: 0x00
0x17
1
AACK_PROM_MODE
1: Enable promiscuous Mode
0x2E
4
AACK_DIS_ACK
1: Disable generation of acknowledgment
0x2E
7:6
AACK_FVN_MODE
Controls the ACK behavior, depending on FCF
frame version number
0x00: acknowledges only frames with version
number 0, i.e. according to IEEE 802.15.4-2003
frames
0x01: acknowledges only frames with version
number 0 or 1, i.e. frames according to
IEEE 802.15.4-2006
0x10: acknowledges only frames with version
number 0 or 1 or 2
0x11: acknowledges all frames, independent of
the FCF frame version number
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| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-16SBD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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