
812
6384E–ATARM–05-Feb-10
AT91SAM9G20
44.3.5
Reset Controller (RSTC)
44.3.5.1
RSTC: Reset During SDRAM Accesses
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while
data are ready to be read on the data bus. The SDRAM maintains the data until the clock
restarts.
If the user Reset is programmed to assert a general reset, the data maintained by the SDRAM
leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
NAND Flash boot functionality, if the system boots out of internal ROM.
NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
Problem Fix/Workaround
1.
Avoid User Reset to generate a system reset.
2.
Trap the User Reset with an interrupt.
In the interrupt routine, Power Down SDRAM properly and perform Peripheral and Processor
Reset with software in assembler.
Example with libV3.
The main code:
//user reset interrupt setting
// Configure AIC controller to handle SSC interrupts
AT91F_AIC_ConfigureIt (
AT91C_BASE_AIC,
// AIC base address
AT91C_ID_SYS,
// System peripheral ID
AT91C_AIC_PRIOR_HIGHEST,
// Max priority
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive
sysc_handler );
// Enable SYSC interrupt in AIC
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
*AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN;
The C SYS handler:
extern void soft_user_reset(void);
void sysc_handler(void){
//check if interrupt comes from RSTC
if( (*AT91C_RSTC_RSR & AT91C_RSTC_URSTS ) == AT91C_RSTC_URSTS){
soft_user_reset();
//never reached
while(1);
}