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181
8246B–AVR–09/11
ATtiny2313A/4313
20.3.1
Calibration Byte
The signature area of the ATtiny2313A/4313 contains two bytes of calibration data for the inter-
nal oscillator. The calibration data in the high byte of address 0x00 is for use with the oscillator
set to 8.0 MHz operation. During reset, this byte is automatically written into the OSCCAL regis-
ter to ensure correct frequency of the oscillator.
There is a separate calibration byte for the internal oscillator in 4.0 MHz mode of operation but
this data is not loaded automatically. The hardware always loads the 8.0 MHz calibration data
during reset. To use separate calibration data for the oscillator in 4.0 MHz mode the OSCCAL
register must be updated by firmware. The calibration data for 4.0 MHz operation is located in
the high byte at address 0x01 of the signature area.
20.3.2
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space.
For the ATtiny2313A the signature bytes are:
1.
0x000: 0x1E (indicates manufactured by Atmel).
2.
0x001: 0x91 (indicates 2KB Flash memory).
3.
0x002: 0x0A (indicates ATtiny2313A device when 0x001 is 0x91).
For the ATtiny4313 the signature bytes are:
1.
0x000: 0x1E (indicates manufactured by Atmel).
2.
0x001: 0x92 (indicates 4KB Flash memory).
3.
0x002: 0x0D (indicates ATtiny4313 device when 0x001 is 0x92).
20.4
Reading Lock Bits, Fuse Bits and Signature Data from Software
Fuse and lock bits can be read by device firmware. Programmed fuse and lock bits read zero.
In addition, firmware can also read data from the device signature imprint table. See
“Device20.4.1
Lock Bit Read
Lock bit values are returned in the destination register after an LPM instruction has been issued
within three CPU cycles after RFLB and SPMEN bits have been set in SPMCSR (see
page 176).The RFLB and SPMEN bits automatically clear upon completion of reading the lock bits, or if no
LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within
four CPU cycles. When RFLB and SPMEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
1.
Load the Z-pointer with 0x0001.
2.
Set RFLB and SPMEN bits in SPMCSR.
3.
Issue an LPM instruction within three clock cycles.
4.
Read the lock bits from the LPM destination register.