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147
8246B–AVR–09/11
ATtiny2313A/4313
BAUD
Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRR
Contents of the UBRRH and UBRRL Registers, (0-4095)
15.4
SPI Data Modes and Timing
There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHA and UCPOL. The data transfer timing diagrams are
shown in
Figure 15-1. Data bits are shifted out and latched in on opposite edges of the XCK sig-
nal, ensuring sufficient time for data signals to stabilize. The UCPOL and UCPHA functionality is
summarized in
Table 15-2. Note that changing the setting of any of these bits will corrupt all
ongoing communication for both the Receiver and Transmitter.
Figure 15-1. UCPHA and UCPOL data transfer timing diagrams.
15.5
Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM
mode has two valid frame formats:
8-bit data with MSB first
8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete
frame is transmitted, a new frame can directly follow it, or the communication line can be set to
an idle (high) state.
The UDORD bit in UCSRC sets the frame format used by the USART in MSPIM mode. The
Receiver and Transmitter use the same setting. Note that changing the setting of any of these
bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 15-2.
UCPOL and UCPHA Functionality-
UCPOL
UCPHA
SPI Mode
Leading Edge
Trailing Edge
0
Sample (Rising)
Setup (Falling)
0
1
Setup (Rising)
Sample (Falling)
1
0
2
Sample (Falling)
Setup (Rising)
1
3
Setup (Falling)
Sample (Rising)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0
UCPOL=1
UCPHA=0
UCPHA=1