
19
4378C–AVR–09/08
AT90PWM1
Figure 3. On-chip Data SRAM Access Cycles
6.3
EEPROM Data Memory
The AT90PWM1 contains 512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
“Serial6.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
Table 2. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to
run at a voltage lower than specified as minimum for the clock frequency used. For details on
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
6.3.2
The EEPROM Address Registers – EEARH and EEARL
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
Bit
15
14
13
12
11
10
9
8
–
EEAR8
EEARH