
52
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
9.3.3
GIFR – General Interrupt Flag Register
Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT[5:0] pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in
SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
9.3.4
PCMSK – Pin Change Mask Register
Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Bits 5:0 – PCINT[5:0]: Pin Change Enable Mask 5:0
Each PCINT[5:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[5:0] is
set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[5:0] is
cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit
7
6
5432
10
–
INTF0
PCIF
–––
––
GIFR
Read/Write
R
R/W
R
RRRR
Initial Value
0
0000
00
Bit
765
4321
0
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
PCMSK
Read/Write
R
R/W
Initial Value
000
0000
0