
209
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
18.5.5.1
Parity Checker
The parity checker of the EUSART is available only when data bits are level encoded and behaves as is USART
mode (See Parity checker of the USART).
18.5.5.2
OverRun
The Data OverRun (DOR bit of USCRA) flag indicates data loss due to a receiver buffer full condition. This flag
operates as in USART mode (See USART section).
18.6
EUSART Registers Description
18.6.1
USART I/O Data Register – UDR
Bit 7:0 – RxB7:0: Receive Data Buffer (read access)
Bit 7:0 – TxB7:0: Transmit Data Buffer (write access)
This register is common to the USART and EUSART interfaces for Transmit Data Buffer Register and Receive
Data Buffer Register. See description for UDR register in USART.
18.6.2
EUSART I/O Data Register – EUDR
Bit 7:0 – RxB15:8: Receive Data Buffer (read access)
Bit 7:0 – TxB15:8: Transmit Data Buffer (write access)
This register provide an extension to the UDR register when EUSART is used with more than 8 bits.
18.6.2.1
UDR/EUDR data access with character size up to 8 bits
When the EUSART is used with 8 or less bits, only the UDR register is used for dta access.
18.6.2.2
UDR/EUDR data access with 9 bits per character
When the EUSART is used with 9 bits character, the behavior is different of the standard USART mode, the UDR
register is used in combination with the first bit of EUDR (EUDR:0) for data access, the RxB8/TxB8 bit is not used.
Bit
7
6
5
43
21
0
RXB[7:0]
UDR (Read)
TXB[7:0]
UDR (Write)
Read/Write
R/W
Initial Value
0
Bit
7
6
5
43
21
0
RXB[15:8]
EUDR (Read)
TXB[15:8]
EUDR (Write)
Read/Write
R/W
Initial Value
0
1
0