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83
8183F–AVR–06/12
ATtiny24A/44A/84A
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
11.9.3
TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
11.9.4
OCR0A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
11.9.5
OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
11.9.6
TIMSK0 – Timer/Counter 0 Interrupt Mask Register
Bits 7:3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero.
100
clkI/O/256 (From prescaler)
101
clkI/O/1024 (From prescaler)
1
0
External clock source on T0 pin. Clock on falling edge.
1
External clock source on T0 pin. Clock on rising edge.
Table 11-9.
Clock Select Bit Description (Continued)
CS02
CS01
CS00
Description
Bit
765
432
10
TCNT0[7:0]
TCNT0
Read/Write
R/W
Initial Value
0
Bit
765
432
10
OCR0A[7:0]
OCR0A
Read/Write
R/W
Initial Value
0
Bit
765
432
10
OCR0B[7:0]
OCR0B
Read/Write
R/W
Initial Value
0
Bit
7654
3
2
1
0
––––
–
OCIE0B
OCIE0A
TOIE0
TIMSK0
Read/Write
RRRR
R
R/W
Initial Value
0000
0