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參數(shù)資料
| 型號： | MQ80C154-L16/883R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 47/49頁 |
| 文件大?。?/td> | 61013K |
| 代理商： | MQ80C154-L16/883R |
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140
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
ing the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between
TCNT2 and the OCR2A Register.
18.11.3
OCR2A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2A pin.
18.11.4
TIMSK2 – Timer/Counter2 Interrupt Mask Register
Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Com-
pare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2
occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the
TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.
18.11.5
TIFR2 – Timer/Counter2 Interrupt Flag Register
Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A –
Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes count-
ing direction at 0x00.
Bit
765
432
10
(0xB3)
OCR2A[7:0]
OCR2A
Read/Write
R/W
Initial Value
000
00
Bit
7
65432
1
0
(0x70)
–
OCIE2A
TOIE2
TIMSK2
Read/Write
RRRRR
R
R/W
Initial Value
0
00000
0
Bit
765
432
10
0x17 (0x37)
–
–OCF2A
TOV2
TIFR2
Read/Write
RR
RRR
R
R/W
Initial Value
000
00
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| MQ83C154XXX-L16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MQ83C154CXXX-25/883R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MR80C154-L16/883R | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
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