參數(shù)資料
型號: MQ80C154-L16/883R
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù): 32/49頁
文件大?。?/td> 61013K
代理商: MQ80C154-L16/883R
127
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter value at all times.
The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency out-
put on the Output Compare pin (OC2A). See ”O(jiān)utput Compare Unit” on page 128. for details. The compare match
event will also set the Compare Flag (OCF2A) which can be used to generate an Output Compare interrupt
request.
18.2.2
Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, that is, TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in Table 18-1 are also used extensively throughout the section.
18.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clk
T2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to
logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see ”ASSR – Asynchronous Status Register” on page 141. For details on clock
18.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a
block diagram of the counter and its surrounding environment.
Figure 18-2. Counter Unit, block diagram.
Signal description (internal signals):
count
Increment or decrement TCNT2 by 1.
direction
Selects between increment and decrement.
clear
Clear TCNT2 (set all bits to zero).
clk
T2
Timer/Counter clock.
top
Signalizes that TCNT2 has reached maximum value.
bottom
Signalizes that TCNT2 has reached minimum value (zero).
Table 18-1.
Timer/Counter definitions.
BOTTOM
The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is dependent
on the mode of operation.
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int.Req.)
top
bottom
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
I/O
clk
Tn
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