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參數(shù)資料
| 型號(hào)： | MPT57571B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 384-CHANNEL 256-GRADATION SOURCE DRIVER FOR COLOR TFT LCDS |
| 中文描述： | 384-CHANNEL 256-GRADATION源驅(qū)動(dòng)的彩色TFT液晶顯示器 |
| 文件頁數(shù)： | 4/29頁 |
| 文件大?。?/td> | 350K |
| 代理商： | MPT57571B |
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MPT57571B
384-CHANNEL 256-GRADATION SOURCE DRIVER FOR COLOR TFT LCDS
SGLS110A – FEBRUARY 2000 – REVISED AUGUST 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
FUNCTION
Port 1
Image signal input
terminal
D00–D07
D10–D17
D20–D27
I
Image signal input terminal
Inputs image signals with a 48 bit width: 8 bit gradation data x 6 dots (for 2 pixels)
Inputs image signals with a 48-bit width: 8-bit gradation data x 6 dots (for 2 pixels).
Dn0: LSB, Dn7: MSB
D30–D37
D40–D47
D50–D57
Port 2
Image signal input
terminal
I
Internal shift register’s start pulse I/O terminal
EIO1
EIO2
Start pulse I/O
terminal
I/O
L/R = H
Right-shift input
L/R =L
EIO1
Left-shift output
EIO2
Right-shift output
Left-shift input
L/R
Shift direction
selection signal input
terminal
I
Shift direction selection signal
Right shift (OUT1
→
OUT 384): H
Left shift (OUT384
→
OUT1): L
Shift register transfer clock input terminal. CLK writes the display data to the data register at
the leading edge.
CLK
Shift clock input
terminal
I
VDD1 (*1)
VDD1 (*2)
VSS1
Analog power supply
I
Power supply for analog circuits
VDD1 (*1) is used as the analog circuit reference potential
Stable electric potential must be supplied.
VDD1 (*2) is used for output circuits, etc.
VDD2,
VSS2
Digital power supply
I
Power supply for digital circuits
GMA1...GMA16
Gamma correction
reference potential
input terminal
I
Potential input terminal for gamma correction
Reference potential should be maintained when outputting the gradation voltage.
See recommended operating conditions for potential-related information.
7+7 GMA input is possible by processing GMA11 and GMA6 in the TCP option.
TP1
Latch input terminal
I
Latches the data register contents with the leading edge, transfers it to the D/A converter, and
outputs the gradation voltage with the trailing edge.
POL
Polarity reversal
terminal
I
POL = L: odd-numbered outputs GMA1-GMA8 and even-numbered outputs GMA9-GMA16
are reference power supplies.
POL = H: odd-numbered outputs GMA9-GMA16 and even-numbered outputs GMA1-GMA8
are reference power supplies.
REV1
REV2
Input data reversal
terminal
I
Selects reversal/nonreversal of input data:
REV1: controls reversal/nonreversal of port 1.
REV1: controls reversal/nonreversal of port 2.
REV1,2 = H: reversal
REV1,2 = L: nonreversal
This terminal can be processed within TCP.
H and L are identified at the leading edge of each CLK, like the data (Dxx).
OUT1–OUT384
LCD control output
terminal
O
Subpixel output. OUT1–OUT384 provides 256 gray-scale signals to the LCD panel.
SHC
Output circuit control
signal input terminal
I
Signal used for output circuit control.
RS
LCD drive capacity
switching terminal
I
Switched LCD drive capacity:
RS = H: heavy-load mode
RS = L: spec-load mode
LP
Low-power mode
selection terminal
I
Reduces charge and discharge current to a load:
LP = H: low-power mode
LP = L: normal mode
See application Information for details.
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