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參數(shù)資料
| 型號(hào)： | MPT57571B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 384-CHANNEL 256-GRADATION SOURCE DRIVER FOR COLOR TFT LCDS |
| 中文描述： | 384-CHANNEL 256-GRADATION源驅(qū)動(dòng)的彩色TFT液晶顯示器 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大小： | 350K |
| 代理商： | MPT57571B |
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MPT57571B
384-CHANNEL 256-GRADATION SOURCE DRIVER FOR COLOR TFT LCDS
SGLS110A – FEBRUARY 2000 – REVISED AUGUST 2000
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
V
DD2
= 2.5 V to < 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc1
tw1
tw2
tsu1
th1
tsu2
th2
td1
td2
td3
tsu3
CLK cycle time
See Figure 3
18
ns
High-level CLK pulse width duration
See Figure 3
4
ns
Low-level CLK pulse width duration
See Figure 3
4
ns
Data/REV setup time
See Figure 3
4
ns
Data/REV hold time
See Figure 3
0
ns
Start pulse setup time
See Figure 3
4
ns
Start pulse hold time
See Figure 3
0
ns
Start pulse signal delay time
See Figure 3
10
ns
μ
s
μ
s
ns
LCD drive signal delay time
See Figure 3 and Notes 8 and 10
5
See Figure 3 and Notes 9 and 10
10
TP1 signal E10 (input) setup time
See Figure 3
70
th3
TP1 low hold time from final data CLK
See Figure 3
1
CLK
cycle
tw3
tsu4
th4
th5
tsu5
NOTES:
High-level TP1 signal pulse width duration
See Figure 3
1.5
μ
s
ns
POL signal TP1 setup time
See Figure 3
–5
POL signal TP1 hold time
See Figure 3
6
ns
μ
s
μ
s
SHC hold time
See Figure 4
4.5
SHC setup time
See Figure 4
4.5
8. Specified as the value at which the driver’s output voltage reaches the target output voltage
±
(VDD1 x 0.1).
9. Specified as the value at which the driver’s output voltage reaches the target output voltage (8-bit precision).
10. The load of the analog output terminal is the value shown in Figure 7.
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